SSRG - IJVSP - Volume 5 Issue 3 - September to December 2018

S.No Title/Author Name Paper ID
1.   Increasing Fault Coverage in Benchmark Circuit using Design for Testability and Test Pattern Generation using 6NCA
- Shashank Srivastava, Tanusree Kaibartta
IJVSP-V5I3P101
2.   Increasing Fault Coverage in Benchmark Circuit using Design for Testability and Test Pattern Generation using 3 NCA
- Shashank Srivastava, Tanusree Kaibartta
IJVSP-V5I3P102
3.   Hybrid DFT Method using Genetic Algorithm Based Test Pattern
- Shashank Srivastava, Tanusree Kaibartta
IJVSP-V5I3P103
  Remaining articles are in progress....