SSRG - IJVSP - Volume 5 Issue 3 - September to December 2018

S.No Title/Author Name Paper ID
1.   Increasing Fault Coverage in Benchmark Circuit using Design for Testability and Test Pattern Generation using 6NCA
- Shashank Srivastava, Tanusree Kaibartta
2.   Multiplier Design Incorporating Logarithmic Number System for Residue Number System in Binary Logic
- Shalini R.V, Dr.P.Sampath
3.   Parametric Variations of Transistor Doping Profiles for Ultra Low Power Applications
- Xhino M. Domi, Emadelden Fouad, Muhammad S. Ullah
  Remaining articles are in progress....