FPGA Implementation of BCG Signal Filtering Scheme by using Weight Update Process

International Journal of VLSI & Signal Processing

© 2016 by SSRG - IJVSP Journal

Volume 3 Issue 3

Year of Publication : 2016

Authors : Ms.Manjula B.M and Dr.Chirag Sharma

10.14445/23942584/IJVSP-V3I5P101

How to Cite?

Ms.Manjula B.M and Dr.Chirag Sharma, "FPGA Implementation of BCG Signal Filtering Scheme by using Weight Update Process," SSRG International Journal of VLSI & Signal Processing, vol. 3,  no. 3, pp. 1-7, 2016. Crossref, https://doi.org/10.14445/23942584/IJVSP-V3I5P101

Abstract:

In this work, we propose an efficient architecture for BCG signal filtering using least means square adaptive filter. To achieve the less delay for adaption, less power consumption, we have used optimized pipelining based scheme across the combinational blocks. This scheme uses a new scheme to reduce the delay by updating the weights of the input sample. Updated weights and input samples are passed to the next stage of the filtering before arrival of the next sample. This scheme is implemented for , and filtering scheme using Xilinx ISE simulator performance of the model is evaluated in terms of power delay and frequency. Results shows the efficient performance of the architecture in terms of frequency, for 2-tap, 3-tap and 4-tap filtering scheme, operating frequency is achieved 528.513 MHz.

Keywords:

Results shows the efficient performance of the architecture in terms of frequency, for 2-tap, 3-tap and 4-tap filtering scheme, operating frequency is achieved 528.513 MHz.

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