A VLSI IMPLEMENTATION OF HAMMING CODE ALGORITHM USING FPGA ARCHITECTURE

International Journal of VLSI & Signal Processing

© 2020 by SSRG - IJVSP Journal

Volume 7 Issue 2

Year of Publication : 2020

Authors : Vijayakumara Y M, Byregowda B K, Pradeep Kumar S, Raghav S, Nataraja M, Dr. S N Sheshappa

10.14445/23942584/IJVSP-V7I2P105

How to Cite?

Vijayakumara Y M, Byregowda B K, Pradeep Kumar S, Raghav S, Nataraja M, Dr. S N Sheshappa, "A VLSI IMPLEMENTATION OF HAMMING CODE ALGORITHM USING FPGA ARCHITECTURE," SSRG International Journal of VLSI & Signal Processing, vol. 7,  no. 2, pp. 29-35, 2020. Crossref, https://doi.org/10.14445/23942584/IJVSP-V7I2P105

Abstract:

The communication theory has the issue of error correction, and detection has great practical importance. Error correction codes permit the detection and correction of errors that result from noise or other impairments during transmission from the transmitter to the receiver. Error correction schemes permit error localization and also give the possibility of correcting them. Error correction and detection schemes find use in implementations of reliable data transfer over noisy transmission links, data storage media (including dynamic RAM, compact discs), and other applications where data
integrity is important. Error correction avoids retransmission of the data, which can degrade system performance.
Hamming code is an error-correction code that can be used to detect single and double-bit errors and correct single-bit errors that can occur when
binary data is transmitted from one device into another. Hamming codes provide for FEC using a "block parity" mechanism that can be inexpensively
implemented. In general, their use allows the correction of single-bit errors and detection of two-bit errors per unit data, called a code word.

Keywords:

communication, memory, code correction, Hamming code

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