Address Sequence Generator for Memory BIST

International Journal of Computer Science and Engineering

© 2019 by SSRG - IJCSE Journal

Volume 6 Issue 11

Year of Publication : 2019

Authors : Mikalai Shauchenka

10.14445/23488387/IJCSE-V6I11P112

How to Cite?

Mikalai Shauchenka, "Address Sequence Generator for Memory BIST," SSRG International Journal of Computer Science and Engineering , vol. 6,  no. 11, pp. 55-59, 2019. Crossref, https://doi.org/10.14445/23488387/IJCSE-V6I11P112

Abstract:

In this work a structure that generates memory address sequences for built-in memory self tests is proposed. The idea is to significantly expand the set of address sequences. The structure consists of three components, namely the base address sequence generator, a device for generating and storing a matrix of binary vectors, and a device to calculate the address values. The idea behind this structure is to significantly expand the set ofdifferent address sequences including the standard well known and extensively used sequences for memory testing.

Keywords:

MBIST, Built in memory self-test, pseudo-random numbers, pseudo-random sequences

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