HLS Design of Min Sum Decoding Algorithm on Zynq
|International Journal of Computer Science and Engineering|
|© 2021 by SSRG - IJCSE Journal|
|Volume 8 Issue 7|
|Year of Publication : 2021|
|Authors : Arwa H. Ashou, Dhafir A. Alneema|
How to Cite?
Arwa H. Ashou, Dhafir A. Alneema, "HLS Design of Min Sum Decoding Algorithm on Zynq," SSRG International Journal of Computer Science and Engineering , vol. 8, no. 7, pp. 10-15, 2021. Crossref, https://doi.org/10.14445/23488387/IJCSE-V8I7P102
The Low-Density Parity Check (LDPC) codes are an important aspect of 5 G communication systems. This code is a forward error correction block code that corrects errors by iteratively performing decoding operations. Using High-Level Synthesis (HLS) techniques, however, this paper presents a high-performance Min Sum LDPC decoder. HLS for FPGAs is widely used as a good hardware synthesis tool due to one of the key advantages of FPGAs is flexibility. This paper uses an optimization technique including array partitioning and loop unrolling to minimize latency and increase throughput. The results showed that the implementation speed was increased. For simulation results, Xilinx Vivado HLS 18.3 is used on Zynq-7000 Evaluation Board Part xc7z020clg484-1.
LDPC, Min Sum, FPGA, HLS, ZYNQ.
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