HLS Design of Min Sum Decoding Algorithm on Zynq

International Journal of Computer Science and Engineering

© 2021 by SSRG - IJCSE Journal

Volume 8 Issue 7

Year of Publication : 2021

Authors : Arwa H. Ashou, Dhafir A. Alneema

10.14445/23488387/IJCSE-V8I7P102

How to Cite?

Arwa H. Ashou, Dhafir A. Alneema, "HLS Design of Min Sum Decoding Algorithm on Zynq," SSRG International Journal of Computer Science and Engineering , vol. 8,  no. 7, pp. 10-15, 2021. Crossref, https://doi.org/10.14445/23488387/IJCSE-V8I7P102

Abstract:

The Low-Density Parity Check (LDPC) codes are an important aspect of 5 G communication systems. This code is a forward error correction block code that corrects errors by iteratively performing decoding operations. Using High-Level Synthesis (HLS) techniques, however, this paper presents a high-performance Min Sum LDPC decoder. HLS for FPGAs is widely used as a good hardware synthesis tool due to one of the key advantages of FPGAs is flexibility. This paper uses an optimization technique including array partitioning and loop unrolling to minimize latency and increase throughput. The results showed that the implementation speed was increased. For simulation results, Xilinx Vivado HLS 18.3 is used on Zynq-7000 Evaluation Board Part xc7z020clg484-1.

Keywords:

LDPC, Min Sum, FPGA, HLS, ZYNQ.

References:

[1] R. Gallager., Low-density parity-check codes., IRE Transactions on information theory, 8 (1962) 21-28.
[2] D. J. MacKay and R. M. Neal., Near Shannon limit performance of low-density parity-check codes, Electronics Letters, 32(1996) 1645-1646.
[3] J. Campello, D. S. Modha, and S. Rajagopalan., Designing LDPC codes using bit-filling., in ICC 2001. IEEE International Conference on Communications. Conference Record (Cat. No. 01CH37240) (2001) 55-59.
[4] P.Vemaiah and S.Kannappan., Efficient Performance Analysis of IEEE802.11a Standard in Mobile Environment. SSRG International Journal of Electronics and Communication Engineering., 2 (6) (2015) 1-4.
[5] Shahzeb Hussain, Namrata Bhadri, and Md. Shaayan Hussain., Advancements in Wireless Communication., SSRG International Journal of Electronics and Communication Engineering., 7 (9) (2020) 1-4.
[6] G. Falcao, V. Silva, J. Marinho, and L. Sousa., LDPC decoders for the WiMAX (IEEE 802.16 e) based on multicore architectures., in WIMAX New Developments, ed: IntechOpen, (2009).
[7] H. Gharaee, M. Kiaee, and N. Mohammadzadeh., A high-throughput FPGA implementation of quasi-cyclic LDPC decoder., IJCSNS, 17(2017) 140.
[8] G. Choi, K.-B. Park, and K.-S. Chung., Optimization of FPGA-based LDPC decoder using high-level synthesis, in Proceedings of the 4th International Conference on Communication and Information Processing, (2018) 256-259.
[9] X. Zhang, VLSI architectures for modern error-correcting codes: Crc Press, (2017).
[10] M. C. Davey and D. J. MacKay., Low-density parity-check codes over GF (q), in 1998 Information Theory Workshop (Cat. No. 98EX131), (1998) 70-71.
[11] S. A. Alabady., Binary and non‐binary low-density parity-check codes: a survey., Int J Inf Eng Appl, 1(2018) 104-117.
[12] N. Noorshams and M. J. Wainwright., Stochastic belief propagation: A low-complexity alternative to the sum-product algorithm, IEEE Transactions on Information Theory, 59(2012) 1981-2000.
[13] S. Lin and D. J. Costello, Error control coding., Prentice hall, 2(2001).
[14] K. D. Rao, Channel coding techniques for wireless communications: Springer, (2015).
[15] A. T. Ali and D. A. Alneema., Design Analysis of Turbo Decoder Based on One MAP Decoder Using High-Level Synthesis Tool, Al-Rafidain Engineering Journal (AREJ), 25 (2020) 70-77.
[16] Amer T. Ali and Dhafir A. Alneema., Design and Analysis Combining Two Algorithms in One Turbo Decoder, IJIRCCE, 8(8) (2020).
[17] Y. Liu, W. Tang, and D. G. Mitchell., Efficient Implementation of a Threshold Modified Min-Sum Algorithm for LDPC Decoders, IEEE Transactions on Circuits and Systems II: Express Briefs, 67(2020) 1599-1603.
[18] Q. Yi and Z. Xiaorong., Design of programmable parallel LDPC decoder, in 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN), (2017) 66-70.
[19] S.-W. Choi, G.-P. Kim, and J.-K. Kim., An LDPC decoder architecture for multi-rate QC-LDPC codes, in 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), (2011) 1-4.
[20] L. Romani., Hardware Acceleration of 5G LDPC using datacenter-class FPGAs, Politecnico di Torino, (2020).
[21] R. Anantharaman, K. Kwadiki, and V. P. Kerehalli Shankar Rao., Hardware Implementation Analysis of Min-Sum Decoders, Advances in Electrical and Electronic Engineering, 17(2019) 179-186.
[22] S. Pawankar and N. Mohota., High-Performance LDPC Decoder design using FPGA, in 2019 9th International Conference on Emerging Trends in Engineering and Technology-Signal and Information Processing (ICETET-SIP-19), (2019) 1-4.
[23] J. Zhou and X. Zhang., Algorithmic Obfuscation for LDPC Decoders, arXiv preprint arXiv:2104.03814, (2021).
[24] Y. Li, Z. Qin, L. Zou, Y. Qin, and Q. Lu., Graph-Based Detection and LDPC Decoding over 2D Intersymbol Interference Channels, J. Commun., 16(2021) 91-98.
[25] Z. Qin, Y. Li, Y. Qin, Q. Lu, and X. Liu., Graph-based detection and reduced-complexity LDPC decoding over 2D intersymbol interference channels, in Twelfth International Conference on Signal Processing Systems, (2021) 117190X.
[26] M. Kuc, W. Sułek, and D. Kania., Hardware implementation of the LDPC decoder in the FPGA structure, in AIP Conference Proceedings, (2021) 050002.
[27] B. M. Younis and A. K. Younis., Hardware accelerator for anti-aliasing Wu's line algorithm using FPGA, Telkomnika, 19 (2021) 672-682.
[28] A. Boudaoud, M. El Haroussi, and E. Abdelmounim., VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate., International Journal of Advanced Computer Science and Applications, 8(2017).
[29] S. ZHANG and W. Qi., Joint Design of Quasi-cyclic Low-Density Parity-Check Codes and Performance Analysis of Multi-source Multi-relay Coded Cooperative System, 41(2019) 2325-2333.
[30] T. Heidari and A. Jannesari., Design of high-throughput QC-LDPC decoder for WiMAX standard, in 2013 21st Iranian Conference on Electrical Engineering (ICEE), (2013) 1-4.
[31] M. R. Islam, D. S. Shafiullah, M. M. A. Faisal, and I. Rahman., Optimized min-sum decoding algorithm for low-density parity-check codes., International Journal of Advanced Computer Science and Applications, 2(2011) 168-174.
[32] V. A. Chandrasetty and S. M. Aziz., An area-efficient LDPC decoder using a reduced complexity min-sum algorithm, Integration, 45(2012) 141-148.
[33] X. Chen and C.-L. Wang., High-throughput efficient non-binary LDPC decoder based on the simplified min-sum algorithm, IEEE Transactions on Circuits and Systems I: Regular Papers, 59(2012) 2784-2794.