12 bit Time Interleaved ADC in 65nm Technology

International Journal of Electronics and Communication Engineering

© 2015 by SSRG - IJECE Journal

Volume 2 Issue 10

Year of Publication : 2015

Authors : R.P.Sheetal and Ameet Chavan

10.14445/23488549/IJECE-V2I10P102

How to Cite?

R.P.Sheetal and Ameet Chavan, "12 bit Time Interleaved ADC in 65nm Technology," SSRG International Journal of Electronics and Communication Engineering, vol. 2,  no. 10, pp. 1-7, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I10P102

Abstract:

This paper presents an architecture of a 4- Time Interleaved ADC (TIADC) having sampling rate of 2GSps and resolution of 12-bit. The input signal is sampled at 2GHz with aid of a 4-phase clock generator providing a 90° phase shift. The design is operated at 1.2-V power supply with digital control running at frequency of 1.953MHz. The designed TIADC has a 2GS/s sampling rate, ENOB of 11.21b, SNDR of 69.249 dB, SFDR of 79.09 dB and consumes total power of 40.32 mW. The TIADC architecture is implemented using UMC 65nm CMOS technology.

Keywords:

Analog to digital converter (ADC), Time interleaving, sampling rate, resolution, CMOS, ENOB, SNDR, SFDR

References:

[1] Mikael Gustavsson, “CMOS data converters for communications”, Kluwer Academic Publishers.
[2] Behzad Razavi, “Design Considerations for Interleaved ADCs,” IEEE JOURNAL OF STATE CIRCUITS, VOL. 48, NO. 8, AUGUST 2013.
[3] C.-C. Huang, C.-Y. Wang, and J.-T. Wu, “A CMOS 6-bit 16- GS/s time-interleaved ADC using digital background calibration techniques,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 848–858, Apr.2011.
[4] M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838–847, Apr. 2011.
[5] K. Doris et al., “A 480 mW 2.6 GS/s 10b 65 nm time-interleaved ADC with 48.5 dB SNDR up to Nyquist,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011.
[6] Verbruggen et al., “A 2.6 mW 6b 2.2 GS/s 4-times interleaved fully dynamic pipelined ADC in 40 nm digital CMOS,” in IEEE ISSCC Dig., 2010, pp. 296–297.
[7] Stepanovic and B. Nikolic, “A 2.8-GS/s 44.6-mW timeinterleaved ADC achieving 50.9 SNDR and 3-dB effective resolution bandwidth of 1.5 GHz in 65-nm CMOS,” in Proc. Symp. VLSI Circuits Dig. Tech.Papers, Jun. 2012, pp. 84–85.
[8] Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7-mW 11-b 250-MS/s 2x interleaved fully dynamic pipelined SAR ADC in 40-nm digital CMOS,” in Proc. ISSCC Dig. Tech. Papers,Feb. 2012, pp.466–467.
[9] J. Guerber et al., “A 10-b ternary SAR ADC with quantization time information utilization,” IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2604–2613, Nov. 2012.
[10] C.-Y. Chen et al., “A 12-bit 3-GS/s pipeline ADC with 0.4 mm and 500 mW in 40-nm digital CMOS,” no. 4, pp. 1013–1021, Apr. 2012.
[11] Y. T. Wang and B. Razavi, “An 8-bit 150-MHz CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 308– 17, Mar. 2000.