Design of Low Power Digit-serial Adder Filter

International Journal of Electronics and Communication Engineering

© 2015 by SSRG - IJECE Journal

Volume 2 Issue 10

Year of Publication : 2015

Authors : Pritesh R. Gumble and Dr.S.A.Ladhake

10.14445/23488549/IJECE-V2I10P103

How to Cite?

Pritesh R. Gumble and Dr.S.A.Ladhake, "Design of Low Power Digit-serial Adder Filter," SSRG International Journal of Electronics and Communication Engineering, vol. 2,  no. 10, pp. 8-11, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I10P103

Abstract:

In the occurrence of DSP applications the weighted operations are the multiplication and accumulation. Multiplier-Accumulator (MAC) unit that consumes low power is always a means to achieve a high performance digital signal processing system. Finite impulse response (FIR) filters are widely used in various DSP applications like data converters. Until many proficient techniques have been introduced for the design of low snag bit-parallel multiple constant multiplications (MCM) process which reduces the complexity of many digital signal processing systems. On the other hand, digit-serial adder architectures present remarkable n-bit designs which process dynamic size data, since digit-serial operators hold less area and power. The purpose of this work is to design and implementation of low power optimized digital Finite impulse response (FIR) filter architecture using VLSI technique. We design and analyze Transpose using MCM and digit serial adder. Experimental results found best performance results of Transpose using MCM and digit serial adder design in terms of area and power.

Keywords:

Digit- serial adder architecture, FIR, Low Power, MAC, MCM.

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