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Volume 13 | Issue 4 | Year 2026 | Article Id. IJECE-V13I4P110 | DOI : https://doi.org/10.14445/23488549/IJECE-V13I4P110

Data Path Reallocation and Silicon Footprint Minimization for a 4-Bit ALU Using E-FRIMA and DW-FGCG Techniques

Shylaja V, N. Kannan, T. Y. Satheesha

Received Revised Accepted Published
09 Jan 2026 10 Feb 2026 11 Mar 2026 30 Apr 2026

Citation :

Shylaja V, N. Kannan, T. Y. Satheesha, "Data Path Reallocation and Silicon Footprint Minimization for a 4-Bit ALU Using E-FRIMA and DW-FGCG Techniques," International Journal of Electronics and Communication Engineering, vol. 13, no. 4, pp. 132-146, 2026. Crossref, https://doi.org/10.14445/23488549/IJECE-V13I4P110

Abstract

Minimizing silicon footprint and optimizing transistor count are important for improving the power efficiency and performance while designing the 4-bit Arithmetic Logic Unit (ALU). Yet, conventional studies have not performed data path reallocation in ALU, which has increased its resource utilization and power consumption. Thus, this paper presents an efficient Excoffier Functional Redundancy Identification and Merging Algorithm (E-FRIMA) and Drop wave Fine-Grained Clock Gating (Dw-FGCG)-based design of data path reallocation and silicon footprint minimization-aware 4-bit ALU. Initially, for performing ALU operations, the functional requirements are provided. Next, by employing the Zagros Karnaugh Map (ZKM), logic level reduction is done. After constructing the map, data path reallocation is performed based on E-FRIMA to reduce resource utilization and power consumption. Then, by using Return-To-Zero Asynchronous Logic (RTZ-AL), the errors in the reallocated data path are minimized. Now, through Dw-FGCG, the transistor receives a clock signal, thereby enabling the clock signal when needed and disabling it when not in use. Next, by using the Power-Skewed Gaussian Adaptive Network-based Fuzzy Inference System (PS-GANFIS), the defects are identified. After that, based on Chen Bird Baker Crayfish Clock Tree Synthesis Optimization (C2B-2CTSO), the identified defects are mitigated. Eventually, a 4-bit ALU design with minimized silicon footprint is obtained. As per the experimental outcomes, the proposed framework reduced the area to 76%, thus outperforming existing methods.

Keywords

Data Path Reallocation, 4-bit Arithmetic Logic Unit (ALU), ALU Area Overhead Reduction, Logic Level Reduction, Zagros Karnaugh Map (ZKM).

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