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Volume 13 | Issue 4 | Year 2026 | Article Id. IJECE-V13I4P118 | DOI : https://doi.org/10.14445/23488549/IJECE-V13I4P118

Machine Learning-Based Wirelength Prediction Using Early Netlist Features for Efficient VLSI Floor-Planning

Kondakamarla Mahammad Ashraf, Gutti Nagaswetha

Received Revised Accepted Published
14 Jan 2026 15 Feb 2026 18 Mar 2026 30 Apr 2026

Citation :

Kondakamarla Mahammad Ashraf, Gutti Nagaswetha, "Machine Learning-Based Wirelength Prediction Using Early Netlist Features for Efficient VLSI Floor-Planning," International Journal of Electronics and Communication Engineering, vol. 13, no. 4, pp. 222-232, 2026. Crossref, https://doi.org/10.14445/23488549/IJECE-V13I4P118

Abstract

Floor-planning is one of the most important phases in the VLSI design technique because it decides the physical configuration of logic blocks, which proves the foundation for the ensuing stages of the fabrication process. The decision process at this phase cannot turn around essential design metrics like silicon deployment, performance parameters, and overall routing effort. Exactly estimating the wirelength before a placement approach is available. Classic estimation methods, including the Rectilinear Steiner Minimum Tree (RSMT) and Half-Perimeter Wirelength (HPWL) model, try to design routing length, but are based on solid geometric simplifications, thus cannot provide useful information when faced with remarkably interconnected and abnormal netlists. This study presents a novel machine-learning method that predicts wirelength using netlist features involving the number of modules, net degree, and spatial metrics. The combined architecture has evolved, and it includes Multi-Layer Perceptron (MLP) and Graph Neural Network (GNN), thus specified as the MLP-GNN. The Tabular features are studied using the MLP component, and graph-using geometric inputs are taken into consideration using the GNN. Experimental evaluations demonstrate that the hybrid MLP-GNN is better than standard baselines, such as MLP, Random Forest, XG Boost, SVR, and the state-of-the-art estimators, with an R2 of 0.89 and a mean absolute error of 40.50 on ISCAS89, ITC99, and synthetic data. The displayed technique allows for efficient design, as it delivers more scalable and placement-free predictions. The hybrid MLP-GNN strikes a balance between a structural approach and the model's computing efficiency as compared to methods based on the use of reinforcement learning. Because of this, it can lower computing costs while maintaining high accuracy in early-stage electrical design automation (EDA) applications.

Keywords

Graph Neural Network, Hybrid MLP-GNN , Netlist Features , Wirelength Estimation , VLSI Floor-planning.

References

  1. Yan Xing et al., “Concurrent Prediction of Timing and Wire Length Using a Multi-Task Graph Neural Network,” ACM Transactions on Design Automation of Electronic Systems, vol. 30, no. 4, pp. 1-20, 2025.
    [    CrossRef] [Google Scholar] [Publisher Link]
  2. Cheong Zheng Quan, Ab Al-Hadi Ab Rahman, and Mohd Shahrizal Rusli, “A Novel Approach in Estimating Wirelength in VLSI Placement Using Machine Learning,” International Conference on Signal, Machines, Automation, and Algorithm, pp. 35-47, 2023.
    [    CrossRef] [Google Scholar] [Publisher Link]
  3. Qinghua Liu, and Malgorzata Marek-Sadowska, “Pre-Layout Wirelength and Congestion Estimation,” Proceedings of the 41st Annual Design Automation Conference, pp. 582-587, 2004.
    [    CrossRef] [Google Scholar] [Publisher Link]
  4. Daeyeon Kim et al., “Machine Learning Framework for Early Routability Prediction With Artificial Netlist Generator,” 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, pp. 1809-1814, 2021.
    [    CrossRef] [Google Scholar] [Publisher Link]
  5. Yunfan Zuo et al., “Enhanced TransUNet Framework for Predicting Static IR Drop and Chip Routability,” ACM Transactions on Design Automation of Electronic Systems, vol. 31, no. 4, pp. 1-26, 2025.
    [    CrossRef] [Google Scholar] [Publisher Link]
  6. Vakhtang Janpoladov, “A Machine Learning-Based Post-Route PVT-Aware Power Prediction of Benchmark Circuits at Floorplan Stage of Physical Design,” 2023 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, pp. 1-6, 2023.
    [    CrossRef] [Google Scholar] [Publisher Link]
  7. V. Lakshmi Kiranmai, and B.K.N. Srinivasarao, “A Novel Hybrid Hexagonal Star Topology for On-Chip Interconnection Networks,” Journal of Circuits, Systems and Computers, vol. 32, no. 5, 2023.
    [    CrossRef] [Google Scholar] [Publisher Link]
  8. Kevin Immanuel Gubbi et al., “Survey of Machine Learning for Electronic Design Automation,” Proceedings of the Great Lakes Symposium on VLSI 2022, pp. 513-518, 2022.
    [    CrossRef] [Google Scholar] [Publisher Link]
  9. Dennis Hemker et al., “From Schematics to Netlists—Electrical Circuit Analysis Using Deep-Learning Methods,” Advances in Radio Science, vol. 22, pp. 61-75, 2024.
    [    CrossRef] [Google Scholar] [Publisher Link]
  10. Deepthi Amuru et al., “AI/ML Algorithms and Applications in VLSI Design and Technology,” Integration, vol. 93, 2023.
    [    CrossRef] [Google Scholar] [Publisher Link]
  11. S.N. Adya, and I.L. Markov, “Fixed-Outline Floorplanning through Better Local Search,” Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001, Austin, TX, USA, pp. 328-334, 2001.
    [    CrossRef] [Google Scholar] [Publisher Link]
  12. S.N. Adya, and I.L. Markov, “Fixed-Outline Floorplanning: Enabling Hierarchical Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1120-1135, 2004.
    [    CrossRef] [Google Scholar] [Publisher Link]
  13. H.F. Jyu et al., “Statistical Timing Analysis of Combinational Logic Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 2, pp. 126-137, 1993.
    [    CrossRef] [Google Scholar] [Publisher Link]
  14. Davide Basso et al., “Effective Analog ICs Floorplanning With Relational Graph Neural Networks and Reinforcement Learning,” 2025 Design, Automation & Test in Europe Conference (DATE), Lyon, France, 2024.
    [    CrossRef] [Google Scholar] [Publisher Link]
  15. Patel Rutvikkumar Popatbhai, and Ruchi Gajjar, “Runtime Prediction for VLSI Physical Design Processes Using Machine Learning,” 2024 28th International Symposium on VLSI Design and Test (VDAT), Vellore, India, pp. 1-6, 2024.
    [    CrossRef] [Google Scholar] [Publisher Link]
  16. B.N.B. Ray et al., “Half-Perimeter Wirelength Model for VLSI Analytical Placement,” 2014 International Conference on Information Technology, Bhubaneswar, India, pp. 287-292, 2014.
    [    CrossRef] [Google Scholar] [Publisher Link]
  17. Qi Xu  et al., “GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 10, pp. 3492-3502, 2022.
    [    CrossRef] [Google Scholar] [Publisher Link]
  18. Zhiyao Xie et al., “Preplacement Net Length and Timing Estimation by Customized Graph Neural Network,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 4667-4680, 2022.
    [    CrossRef] [Google Scholar] [Publisher Link]
  19. Shaik Karimullah, D. Vishnu Vardhan, and Syed Javeed Basha, “Floorplanning for Placement of Modules in VLSI Physical Design Using Harmony Search Technique,” Proceedings of the 1st International Conference on Data Science, Machine Learning and Applications, pp. 1929-1936, 2020.
    [    CrossRef] [Google Scholar] [Publisher Link]
  20. Imran Ullah Khan, Nupur Mittal, and Mohd. Amir Ansari, “Applications of VLSI Design in Artificial Intelligence and Machine Learning,” Machine Learning for VLSI Chip Design, pp. 1-17, 2023.
    [    CrossRef] [Google Scholar] [Publisher Link]
  21. Dho Ui Lim, and Heechun Park, “Graph Neural Network-Based Detailed Placement Optimization Framework,” 2024 25th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, pp. 1-6, 2024.
    [    CrossRef] [Google Scholar] [Publisher Link]
  22. Mohamed Ismail, Ali Aidibe, and Soumaya Yacout, “A Graph Neural Network-Based Optimization Framework for Nonconforming Product Recovery in Multistage Manufacturing Systems,” Journal of Intelligent Manufacturing, pp. 1-28, 2026.
    [    CrossRef] [Google Scholar] [Publisher Link]
  23. Maher Marwani, and Georges Kaddoum, “Event-Based Temporal Graph Neural Network for Radio Resource Management,” IEEE Transactions on Wireless Communications, vol. 25, pp. 10855-10868, 2026.
    [    CrossRef] [Google Scholar] [Publisher Link]
  24. K. Danesh, and R. Dharani, “Optimized Double Deep Reinforcement Learning Based Routing Technique for VLSI Circuit Designing,” Journal of Circuits, Systems and Computers, 2026.
    [    CrossRef] [Google Scholar] [Publisher Link]
  25. G. S. Vikram et al., “Random Forest Assisted Floorplanning Optimization in VLSI Design,” 2025 Modern Electronics Devices and Intelligent Communication Systems (MEDCOM), Greater Noida, India, pp. 863-867, 2025.
    [    CrossRef] [Google Scholar] [Publisher Link]
  26. A. Sumalatha et al., “Automated Very Large-Scale Integration (VLSI) Design Using Artificial Intelligence: Energy-Constrained Internet of Things (IoT) Edge Devices,” 2025 IEEE International Conference on Blockchain and Distributed Systems Security (ICBDS), Kolhapur, India, 2025.
    [    CrossRef] [Google Scholar] [Publisher Link]
  27. Tanmayee Ogeti’, and Satheesh Kumar S’, “Power Estimation in VLSI Circuits Using Supervised Machine Learning,” 2025 6th International Conference for Emerging Technology (INCET), BELGAUM, India, pp. 1-10, 2025.
    [    CrossRef] [Google Scholar] [Publisher Link]