Implementation of low power wireless sensor node with fault tolerance mechanism

International Journal of Electronics and Communication Engineering

© 2016 by SSRG - IJECE Journal

Volume 3 Issue 4

Year of Publication : 2016

Authors : R.Divyasharon and Dr.D.Sridharan

10.14445/23488549/IJECE-V3I4P101

How to Cite?

R.Divyasharon and Dr.D.Sridharan, "Implementation of low power wireless sensor node with fault tolerance mechanism," SSRG International Journal of Electronics and Communication Engineering, vol. 3,  no. 4, pp. 1-5, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I4P101

Abstract:

Wireless Sensor Network based solutions have been widely used since it has the potential to increase our ability to monitor and interact with our environment. WSN consist of number of wireless sensor nodes. Therefore, a node should have long time operating capability and efficient energy management. WSN are usually affected by noise which degrades the performance. It may be affected either by random error or burst error. In this paper, a low power sensor node with fault tolerance capability is developed using verilog code. Hamming code and Cyclic Redundancy Check is used for error free communication. The main aim of this project is to implement the design in FPGA because of its reprogramming ability and the power efficiency can be improved significantly in comparison with commercially micro-controller based sensor.

Keywords:

Low power sensor node, verilog, hamming code, cyclic redundancy check, VLSI, FPGA.

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