An FPGA Chip Identification Generator using Configurable Ring Oscillator

International Journal of Electronics and Communication Engineering

© 2016 by SSRG - IJECE Journal

Volume 3 Issue 4

Year of Publication : 2016

Authors : Mehboob Hasan Ahmed, Rutuja Jagtap, Roopal Pantode and Prof. S. S. Phule

10.14445/23488549/IJECE-V3I4P103

How to Cite?

Mehboob Hasan Ahmed, Rutuja Jagtap, Roopal Pantode and Prof. S. S. Phule, "An FPGA Chip Identification Generator using Configurable Ring Oscillator," SSRG International Journal of Electronics and Communication Engineering, vol. 3,  no. 4, pp. 10-14, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I4P103

Abstract:

Chip identification has a wide range of applications including Digital Intellectual Property Protection etc. Physically Unclonable Functions (PUF) are commonly used. This can be obtained by various technics, which generates a unique binary string. It is difficult to maintain repeatability of chip ID generation especially over a wide range of operating conditions. To overcome this problem we proposed utilizing configurable ring oscillators and orthogonal re-initialization method to improve repeatability. An implementation on a Xilinx Spartan-3E. FPGA chip was tested. Experimental results show that the bit flip rate is reduced from 1.5% to approximately 0 at a fixed supply voltage and room temperature over a 20-800 C temperature range and 25% variation in supply voltage, the bit flip rate is reduced from 1.5% to 3.125 * 10-7

Keywords:

 Ring oscillator, Physically Unclonable Functions (PUF), FPGA..

References:

[1] A. Telikepalli, ―Is your FPGA design secure? Xilinx XCELL, vol. Fall, 2003.
[2] KavitaC.Mugali, MinaksheeM.Patil ―Configurable Ring Oscillator for FPGA chip Identification; Technovision- 2014:1st International Conference at SITS, Narhe, Pune on April 5-6, 2014.
[3] R. Pappu, ―Physical one-way functions, Ph.D. dissertation, Massachusetts Institute of Technology, 2001. [4] R. Pappu, B. Recht, J. Taylor, and N. Gershenfeld, ―Physical One-Way Functions, Science, vol. 297, no. 5589, pp. 2026– 2030, 2002.
[5] K. Lofstrom, W. R. Daasch, and D. Taylor, ―IC identification circuit using device mismatch, in Proceedings of the International Solid State Circuits Conference (ISSCC), 2000, pp. 372–373.
[6] J. Guajardo, S. Kumar, G.-J. Schrijen, and P. Tuyls, ―Physical unclonable functions and public-key crypto for FPGA IP protection, in Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on, aug. 2007, pp. 189 –195.
[7] H. Patel, Y. Kim, J. McDonald, and L. Starman, ―Increasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysis, in Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on, September 2009, pp. 391 –396.
[8] J. Anderson, ―A PUF design for secure FPGA-based embedded systems, in Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, jan. 2010, pp. 1 –6.
[9] G. E. Suh and S. Devadas, ―Physical unclonable functions for device authentication and secret key generation, in DAC ’07: Proceedings of the 44th annual Design Automation Conference. NewYork,NY,USA: ACM, 2007, pp. 9–14.
[10] A. Maiti and P. Schaumont, ―Improving the quality of a physical unclonable function using configurable ring oscillators, in Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on, 31 2009-sept. 2 2009, pp. 703 –707.
[11] H. Yu, P. Leong, H. Hinkelmann, L. Moller, M. Glesner, and P. Zipf, ―Towards a unique FPGA-based identification circuit using process variations,‖ in Field Programmable Logic and Applications, 2009. FPL2009. International Conference on, 31 2009-Sept. 2 2009, pp. 397–402.
[12] T. W. Anderson and D. A. Darling, ―Asymptotic theory of certain goodness of fit criteria based on stochastic processes, in Ann. Math. Statist., vol. Volume 23, 1952, pp. 193–212.