Review Paper on Reduced Power Consumption using Flip Flop
International Journal of Electronics and Communication Engineering |
© 2016 by SSRG - IJECE Journal |
Volume 3 Issue 5 |
Year of Publication : 2016 |
Authors : Supriya Kumari and Amit Patni |
How to Cite?
Supriya Kumari and Amit Patni, "Review Paper on Reduced Power Consumption using Flip Flop," SSRG International Journal of Electronics and Communication Engineering, vol. 3, no. 5, pp. 17-20, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I5P112
Abstract:
In this review paper, we are discussing about the idea to minimize the power dissipation and area minimization using flip flops. The flip flop or latch in the circuit that has two stable states and can be used to store state information. A flip flop is a bi-stable multi vibrator. The circuit can be made to change state by signals applied to one or more control input and will have one or more output. As, the biggest challenge for Industry is to reduce power consumption and area minimization. So we have introduced the brief idea of using multi bit flip flop (using D flip flop) and dynamic D flip flop.
Keywords:
Flip flop, clock pulse trigger , power supply, multi bit flip flop, wire length.
References:
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