Design of a 3-T Half Adder
| International Journal of Electronics and Communication Engineering |
| © 2016 by SSRG - IJECE Journal |
| Volume 3 Issue 6 |
| Year of Publication : 2016 |
| Authors : Sruthi.V, Akhila.Raj.K.M, Madhulika.A.R and Ajin.A.S |
10.14445/23488549/IJECE-V3I6P103
How to Cite?
Sruthi.V, Akhila.Raj.K.M, Madhulika.A.R and Ajin.A.S, "Design of a 3-T Half Adder," SSRG International Journal of Electronics and Communication Engineering, vol. 3, no. 6, pp. 5-8, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I6P103
Abstract:
In this paper, we propose a new technique for implementing a half adder circuit consisting of minimum number of transistors (3-T). The W/L ratio is varied to get the required output. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indices and similar operations. Simulated results indicate the performance of proposed half adder over the conventional half adders. Detailed comparison of the simulated results is presentedhere which is done in MultiSim software.
Keywords:
Pass Transistor Logic, 3-T XOR,Logical Effort and Transistor Sizing
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