Optimized Full Parallelism AES Encryption / Decryption

International Journal of Electronics and Communication Engineering

© 2016 by SSRG - IJECE Journal

Volume 3 Issue 6

Year of Publication : 2016

Authors : Vidyashri.M.Chandkavathe and Mrs. Rashmi S Bhaskar

10.14445/23488549/IJECE-V3I6P104

How to Cite?

Vidyashri.M.Chandkavathe and Mrs. Rashmi S Bhaskar, "Optimized Full Parallelism AES Encryption / Decryption," SSRG International Journal of Electronics and Communication Engineering, vol. 3,  no. 6, pp. 9-11, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I6P104

Abstract:

Cryptography is the art and technology of accomplishing security by using encoding messages to cause them to readable. In today’s world Advanced Encryption Standard (AES) is widely used symmetric key encryption standard. Different architectural models are implemented in this paper. These implemented models adopt task level and data level parallelism so as to increase the performance. The proposed architecture utilizes parallelism to reduce the latency between the processors thus achieving higher speed and throughput. Compared to other different architectural model full parallelism achieves higher throughput and better performance.

Keywords:

symmetric key, data level parallelism, task level parallelism, Advanced Encryption Standard (AES).

References:

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