Ethernet MAC Verification with Loopback Mechanism using Efficient Verification Methodology
| International Journal of Electronics and Communication Engineering |
| © 2016 by SSRG - IJECE Journal |
| Volume 3 Issue 11 |
| Year of Publication : 2016 |
| Authors : Sridevi Chitti, P Chandrasekhar and M Asharani |
10.14445/23488549/IJECE-V3I11P115
How to Cite?
Sridevi Chitti, P Chandrasekhar and M Asharani, "Ethernet MAC Verification with Loopback Mechanism using Efficient Verification Methodology," SSRG International Journal of Electronics and Communication Engineering, vol. 3, no. 11, pp. 16-19, 2016. Crossref, https://doi.org/10.14445/23488549/IJECE-V3I11P115
Abstract:
This paper describes Efficient Verification Methodology (EVM) based constrained random verification (CRV) of a SoC. SoC taken into consideration is Ethernet MAC module with loopback mechanism using XGMII interface. The environment of verification, which is created by means of efficient verification methodology for system verilog is scalable, predictable and reusable and can reduce verification time. Using this verification environment, existence of bugs in the design can be found and design errors with corner cases can be easily located by the help of constraints
Keywords:
Efficient verification methodology, MAC, Verification IP, constrained random verification, Gigabit Ethernet, XGMII.
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