Design of Optimized High Speed FIR Filter
|International Journal of Electronics and Communication Engineering|
|© 2017 by SSRG - IJECE Journal|
|Volume 4 Issue 1|
|Year of Publication : 2017|
|Authors : V.N. Mahawadiwar and S. S. Shriramwar|
How to Cite?
V.N. Mahawadiwar and S. S. Shriramwar, "Design of Optimized High Speed FIR Filter," SSRG International Journal of Electronics and Communication Engineering, vol. 4, no. 1, pp. 1-4, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I1P101
For high performance and portable applications, Energy efficiency is one of the most required features for modern electronics systems design. This article proposes the implementation of FIR Filter using low power adder and multipliers. The ever increasing market segment of portable electronics devices demands the availability of low power building blocks. With the explosive growth in Laptops, portable personal communication systems and evaluation of the shrinking technology and flexible circuits, the efforts in low power micro electronics has been identified. In this scheme the function of adder is minimized by a technique called scaling and rounding-off Filter coefficient and truncation of unnecessary bits in order to reduce the power consumption of FIR Filter. Evaluation of power, area and speed for different types of adders and multipliers is carried out and the FIR filter is designed with optimized combination of adders and multipliers for low power and high speed application. The Full Adder designed with multiplexers do not exhibit any leakage problems and short circuits problems. The current trend towards low-power design is mainly driven by two forces, the growing demand for long-life autonomous portable equipment and the technological limitations of high- performance VLSI systems. The proposed Design of High Speed FIR Filter for DSP Application with Optimized Adder & Multiplier is simulated using Active HDL and implemented using Tanner tool.
FIR filter, Tanner Tool Adder, Multiplier, MAC.
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