Design of Optimized High Speed FIR Filter

International Journal of Electronics and Communication Engineering

© 2017 by SSRG - IJECE Journal

Volume 4 Issue 1

Year of Publication : 2017

Authors : V.N. Mahawadiwar and S. S. Shriramwar

10.14445/23488549/IJECE-V4I1P101

How to Cite?

V.N. Mahawadiwar and S. S. Shriramwar, "Design of Optimized High Speed FIR Filter," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 1, pp. 1-4, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I1P101

Abstract:

For high performance and portable applications, Energy efficiency is one of the most required features for modern electronics systems design. This article proposes the implementation of FIR Filter using low power adder and multipliers. The ever increasing market segment of portable electronics devices demands the availability of low power building blocks. With the explosive growth in Laptops, portable personal communication systems and evaluation of the shrinking technology and flexible circuits, the efforts in low power micro electronics has been identified. In this scheme the function of adder is minimized by a technique called scaling and rounding-off Filter coefficient and truncation of unnecessary bits in order to reduce the power consumption of FIR Filter. Evaluation of power, area and speed for different types of adders and multipliers is carried out and the FIR filter is designed with optimized combination of adders and multipliers for low power and high speed application. The Full Adder designed with multiplexers do not exhibit any leakage problems and short circuits problems. The current trend towards low-power design is mainly driven by two forces, the growing demand for long-life autonomous portable equipment and the technological limitations of high- performance VLSI systems. The proposed Design of High Speed FIR Filter for DSP Application with Optimized Adder & Multiplier is simulated using Active HDL and implemented using Tanner tool.

Keywords:

 FIR filter, Tanner Tool Adder, Multiplier, MAC.

References:

[1] M. Kathirvelu, T. Manigandam, “Design of low power, High speed FIR Filter with optimized PDP Adders and Flip-Flops for DSP Applications”, European Journal of Scientific Research ISSN 1450- 216X Vol. 76 No.2 (2012), pp 214-225.
[2] “CMOS Full-Adders for Energy-Efficient Arithmetic Applications”, of Mariano Aguirre- Hernandez and Monico Linares-Aranda. IEEE Transactions on very large scale integration (VLSI) systems, Vol. 19 No. 04, April 2011.
[3] Hosseinghadiry.M, Mohammadi.H, Nadisenejani.M " Two New low power High Performance Full adders with minimum gates" International journal of Electronics, Circuits and System, vol 3 ,No2 2009. pp. 124 - 131.
[4] Yingtao Jiang, Abdulkarim AI - Sheraidah, Yuke Wang, Edwin Sha,and Jin-Gyun Chung, 2010, " A novel multiplxer based low power full adder" IEEE transaction on circuits and systems - II Express Briefs, Vol52, No 7 `pp- 55-61.
[5] Zaid Al-bayati , Bassam Jamil Mohd, Sahel Alouneh Low power Wallace multiplier design based on wide counters International Journal of Circuit Theory and Applications MAY 2011 issue1 pp 26 - 32.
[6] Weste N. and Eshraghian , 1993, "Principles of CMOS VLSI Design:" A System Perspective. MA: Addison- Wesley.
[7] Senthilpari .S, "A Low-power and High-performance Radix-4 Multiplier Design Using a Modified Pass-transistor Logic Technique" IETE journal of Research, 2011 , Volume 57 Issue 2, PP 149-155.
[8] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, A Design Perspective, Prentice Hall, second edition, 2003.
[9] Proakis J.G and Manolakis D.G, Digital Signal Processing - Principles, Algorithms and Applications New Delhi: Prentice-Hall, 2000.
[10] Rajendra M, Patrikar.K,Murali, Li Er Ping, "Thermal distribution calculations for block level placement in embedded systems" Micro electronics Reliability 44(2004) 129- 134.
[11] Chi-Jui Chou, Satish Mohanakrishnan, Joseph B. Evans, Telecommunications & Information Sciences Laboratory Department of Electrical & Computer Engineering University of Kansas Lawrence, KS 66045-2228, FPGA Implementation of Digital Filters”.
[12] Abdul karim al-sheridha,yingto jiang and Edwin sha 2010,”a novel power multiplexer- based full adder ,European conference on circuit theory and design, august 28-31 espoo,finland.
[13] Jing H.T. bui y.w. ang and design and anylesis of low power 10- transistor full adder using novel xor xnor gates.IEEE trans on circuit and system-II analog and digital signal processing(200) vol49,pp25- 30.
[14] Keivan navi and omid kavehei, February 2008,”low power and high performance 1-bit cmos full adder cell”journal of computers,vol3,no 2pp 36-41
[15] Keivan navi and omid kavehel,2008”design of high –performance full adder cell by combining common digital gates and majority function” European journal pf science research issn1450-216x vol no4,pp626- 638.
[16] Monico linares aranda mariano Aguirre Hernandez new high performance full adder using alternative logic structure,computation and systems vol14.no.3 2011 pp213-223.
[17] Parks t w and burrus c.s. digital filter design new York wiley1987.
[18] Prokies t.w. and burrus c s digital filter design new York wiley 1987
[19] Proakis j.g. manolakis d.g. digital signal processing-principles,algorithms and application new delhi prentice-hall2000
[20] Veeramachaneni ,M.B.Srinivas,”new improved 1 bit full adder cell”CCECE/CGEI,Canada 2009,pp45-51.