An Efficient Bandwidth Utilized FFT Computation using Highly Accelerated Advanced Multiplier

International Journal of Electronics and Communication Engineering

© 2017 by SSRG - IJECE Journal

Volume 4 Issue 3

Year of Publication : 2017

Authors : M. Jyothi Poorna, M.D. Kamala Sri and D. Tejaswi

10.14445/23488549/IJECE-V4I3P108

How to Cite?

M. Jyothi Poorna, M.D. Kamala Sri and D. Tejaswi, "An Efficient Bandwidth Utilized FFT Computation using Highly Accelerated Advanced Multiplier," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 3, pp. 9-12, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I3P108

Abstract:

 During last decades demand for integrated circuits design increases in order to meet the requirement of High speed, High throughput and area efficient. In Digital Signal Processing systems Fast Multipliers are essential. The speed of the multiplication is important not only in digital signal processing but also in general purpose processors. Here a Fast Fourier transform is implement using twin precision technique. By adapting efficient multipliers to the bit widths of the operands reduce the dissipation of power. Computational throughput is increased by performing narrow-width operation in parallel. Efficient bandwidth utilization can be achieved by using twin-precision technique with Baugh-Wooley algorithm.

Keywords:

Fast Fourier Transform, Baugh-Wooley Algorithm, Twin precision.

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