Analytical Modeling of Dual Material Junctionless Surrounding Gate MOSFET
|International Journal of Electronics and Communication Engineering|
|© 2017 by SSRG - IJECE Journal|
|Volume 4 Issue 3|
|Year of Publication : 2017|
|Authors : S.Archana, G.Vallathan and M.Anantha Kumar|
How to Cite?
S.Archana, G.Vallathan and M.Anantha Kumar, "Analytical Modeling of Dual Material Junctionless Surrounding Gate MOSFET," SSRG International Journal of Electronics and Communication Engineering, vol. 4, no. 3, pp. 22-25, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I3P111
The conventional MOSFET is heavily affected by the short channel effects.These effects can be reduced by means of multigate MOSFET. But even in multi gate MOSFET, there is a presence of effects such as threshold voltage roll off, drain induced barrier lowering and difficulties due to the fabrication process.To simplify fabrication process, the technology named asjunctionless transistors arises. Surrounding gate MOSFET is the promising structure for minimizing the occupied area and also the reduction of power consumption. By considering the benefits of all those existing model, the analytical modeling of Junctionless surrounding gate MOSFET is derived.Also by taking the dual material advantages, a technology named as dual material junctionless surrounding gate MOSFET is proposed and the equation for surface potential is obtained by applying the boundary conditions in Poisson’s equation. By using that derived equations, various characteristics and behavior of the device such as surface potential, threshold voltage, and subthreshold swing were plotted against length, radius, doping concentration using MATLAB software.
Short channel effects (SCE), Junctionless transistors(JL), Surrounding gate transistors(SGT), Dual material gate(DMG), Dual material junctionless surrounding gate MOSFET(DMJLSGT).
 CW. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain, JP. Colinge, “Junctionless multigate field-effect transistor”, Applied Physics Letters, Vol. 94, pp. 053511:1-2, 2009
 C.W. Lee, I. Ferain, A. Afzalian, R. Yan, N. Dehdashti Akhavan, P. Razavi, J.P. Colinge, “Performance estimation of junctionless multigate transistors”, Solid-State Electronics, Vol. 54, pp. 97-103, 2010
 JP Colinge, CW Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, AM Kelleher, B. McCarthy, R. Murphy, “Nanowire transistors without junctions”, Nature Nanotechnology, Vol. 5, No. 3, pp. 225-229, 2010
 Y.cui, Z.zhong, D.wang, W.wang, and C. M. liebar, “High performance silicon nanowire FET”,Nano Lett., vol. 3, no. 2, pp. 149-152, 2003
 N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, et al.,”High performance fully depleted silicon nanowire gate all around CMOS devices”IEEE electr device ,vol 27, nio 5, pp.383-386,may 2006
 J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, et al., “Nanowire transistors without junctions,” Nat. Nanotechnol.,vol. 5, no. 3, pp. 225–229, Mar. 2010.
 C.-W. Lee, A. N. Nazarov, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, et al., “Low subthreshold slope in junctionless multigate transistor,” Appl. Phys. Lett., vol. 96, no. 10, pp. 102106-1–102106- 3, Mar. 2010.
 C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, et al., “Performance estimation of junctionless multigate transistors,” Solid State Electron., vol. 54, no. 2, pp. 97–103, Feb. 2010.
 C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, et al., “Performance estimation of junctionless multigate transistors,” Solid State Electron., vol. 54, no. 2, pp. 97–103, Feb. 2010
 Ratul K. Baruah, Member, IEEE, and Roy P. Paily, Member, IEEE,” A Dual-Material Gate Junctionless Transistor With Highk Spacer for Enhanced Analog Performance”, vol. 61, no. 1, January 2014