Transistor Network Generation in Combinational Logic Circuits

International Journal of Electronics and Communication Engineering

© 2017 by SSRG - IJECE Journal

Volume 4 Issue 4

Year of Publication : 2017

Authors : Naveen J and Jabez Daniel V D M

10.14445/23488549/IJECE-V4I4P108

How to Cite?

Naveen J and Jabez Daniel V D M, "Transistor Network Generation in Combinational Logic Circuits," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 4, pp. 38-41, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I4P108

Abstract:

Optimizing transistor network represents an efficient way of improvising VLSI circuits. Existing optimization methods are not actually the most effective way to generate optimized network. The method of reducing only number of literals in a given Boolean expression does not actually reduce the transistor count. This paper proposes a graph-based method for minimizing the number of transistor count that compose a network. This proposed method can provide networks with minimum transistor count with irredundant sum-of-products expression as the input. Experimental results produced by the proposed method shows a substantial reduction in the number of transistor used in the networks.

Keywords:

Digital circuit, factorization, graph theory, transistor network.

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