Design and Comparison of various Low power n-T SRAM cells

International Journal of Electronics and Communication Engineering

© 2017 by SSRG - IJECE Journal

Volume 4 Issue 5

Year of Publication : 2017

Authors : Ramya.P, Shankavi.K, Shilpa unki and Sushmitha Nayak M

10.14445/23488549/IJECE-V4I5P107

How to Cite?

Ramya.P, Shankavi.K, Shilpa unki and Sushmitha Nayak M, "Design and Comparison of various Low power n-T SRAM cells," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 5, pp. 20-25, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I5P107

Abstract:

Modern ICs are enormously complicated due to decrease in device size and increase in chip density involving several millions of transistors per chip. The rules for what can and cannot be manufactured leads to a tremendous increase in complexity due to the amount of power dissipation are increased. For high-speed memory applications such as cache, a SRAM is often used. Power consumption is the key parameter for an SRAM memory design (SRAM). In this paper an effort is made to design 6T, 7T, 8T, 9T, 10T, 11T SRAM cells using Cadence 180nm technology. The average power consumption of these SRAM cells are calculated and compared.

Keywords:

Modern IC, Cache, SRAM cells, average power consumption, cadence 180nm technology.

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