Schematic Design and Layout of Flipflop using CMOS Technology

International Journal of Electronics and Communication Engineering

© 2017 by SSRG - IJECE Journal

Volume 4 Issue 7

Year of Publication : 2017

Authors : Sana Ur Rahman and Tarana Afrin Chandel

10.14445/23488549/IJECE-V4I7P103

How to Cite?

Sana Ur Rahman and Tarana Afrin Chandel, "Schematic Design and Layout of Flipflop using CMOS Technology," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 7, pp. 16-18, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I7P103

Abstract:

 In this paper the work is done on low power and high speed design of flipflop using CMOS technology on different nanoscale technologies i.e. 90 nm, 65nm and 45 nm. The transistor used small area and low power consumption. By decreasing the geometrical feature size of the transistors we can achieve the low power consumption and high speed of integrated circuit in VLSI design. When the technology size decreases in the result of this the leakage power increases which is reduced by type of CMOS technology. The comparisons are held TSPC D-Flipflop and Multi threshold CMOS technology and among the power consumption propagation delay and power dissipation product. The work is carried out with the help of tanner EDA tool.

Keywords:

CMOS technology, Nanoscale technology, VLSI design, Tanner EDA tool.

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