Minimization of Power for the Design of an Optimal Flip Flop

International Journal of Electronics and Communication Engineering

© 2017 by SSRG - IJECE Journal

Volume 4 Issue 7

Year of Publication : 2017

Authors : Kahkashan Ali and Tarana Afrin Chandel

10.14445/23488549/IJECE-V4I7P105

How to Cite?

Kahkashan Ali and Tarana Afrin Chandel, "Minimization of Power for the Design of an Optimal Flip Flop," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 7, pp. 19-25, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I7P105

Abstract:

The power consumption is critically the most important factor in the modern VLSI circuits especially for those circuits which work on low-power applications. This designing aims in achieving optimum speed performance for low power and low noise simultaneously. In this paper basically we are dealing with the power minimization factor. In modern VLSI circuits power saving plays the vital role especially for the applications which runs on low power such as latches, flip-flops and also some logic components which plays a vital role in the functioning of digital system. The main factor is to reduce the power loss in both the flip-flops and clock distribution networks. In this paper we have made a comparison in terms of power loss, parasitic values and no. of transistors in some of the existing classes of the flipflop. Each flip-flop have been analysed and the output is simulated using Tanner EDA tool in 180nm technology. The comparison made shows the best result between the working design of the flip-flop and the existing flip-flop designs.

Keywords:

Tanner EDA, clock distribution networks, Flip flops and Power minimization, pulse triggered.

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