Des IGN of Inexact Circuits using Gate-Level Pruning

International Journal of Electronics and Communication Engineering

© 2017 by SSRG - IJECE Journal

Volume 4 Issue 12

Year of Publication : 2017

Authors : Thilagavathy M. S and Dr. S. GopalaKrishnan

10.14445/23488549/IJECE-V4I12P101

How to Cite?

Thilagavathy M. S and Dr. S. GopalaKrishnan, "Des IGN of Inexact Circuits using Gate-Level Pruning," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 12, pp. 1-3, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I12P101

Abstract:

Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency . Such strategy is suitable for error-tolerant applications involving perceptive or statistical outputs. The gate-level pruning (GLP) is first demonstrated on adders and then Probabilistic pruning technique has been proposed for an efficient approximate tangent function. The approximation is based on a mathematical analysis considering the maximum allowable Significance-Activity Product (SAP) and unessential nodes. This significant saving is achieved by the pruned arithmetic circuits, which sets some nodes to constant values. The proposed approximation scheme is presented, which shows that the proposed structure compares favorably with previous architectures in terms of area, power and delay.

Keywords:

GLP, SAP, Pruned Arithmetic Circuits, DCT, Hyperbolic tangent, Neural Network, Activation Function.

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