Null Convention Logic (NCL) Design of Efficient Sorting Unit

International Journal of Electronics and Communication Engineering
© 2017 by SSRG - IJECE Journal
Volume 4 Issue 12
Year of Publication : 2017
Authors : E. Juhi Gladies and E. Thanga selvi
How to Cite?

E. Juhi Gladies and E. Thanga selvi, "Null Convention Logic (NCL) Design of Efficient Sorting Unit," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 12, pp. 4-7, 2017. Crossref,


 Sorting is a method through which the data is assembled in ascending or descending order. To construct a sorting unit of N values from M inputs. The basic OR, AND gate are used to construct a sorting unit. NCL threshold gates are a specialized case of the logical operands or gates. Self-timed logic design process are developed using Threshold Combinational Reduction (TCR) in the Null Convention Logic (NCL) paradigm. NCL logic functions are constructed using 27 distinct transistor built-up networks. To implement partial sorting using NCL and max-set-selection units with low delay units. But, higher-speed estimation usually raises power consumption extremely. To reduce that problem, a low-power, high-throughput, and modular design of partial sorting network is presented. This paper presents the NCL threshold logic has been used in sorting techniques. The proposed technique is used for lower power consumption and high operating speed. All the circuits in null conventional logic is developed using Threshold Combinational Reduction (TCR) method. Overall NCL logic techniques are meant for reduced area and delay of sorted output.



Null convention logic (NCL), Threshold combinational reduction (TCR),delay insensitive, sorting network, Multi threshold complementary metal oxide semiconductor (MTCMOS) ,Threshold gates.


[1] Matheus T. Moreira and Carlos H. M. Oliveira, ―Design of NCL Gates with the ASCEnD Flow, IEEE Trans.2013.
[2] Andrew D. Bailey, Jia Di, ―Ultra-Low Power Delay- Insensitive Circuit Design, IEEE Trans.2008.
[3] Farhad A. Parsan and Scott C. Smith, ―CMOS Implementation Comparison of NCL Gates IEEE Trans.2012.
[4] Ka Lok Man, Nan Zhang, Chi-Un Lei and Eng Gee Lim, ―Specification and Analysis of Null Convention Logic (NCL) Circuits Using PAFSV, International Multi Conference of Engineers and Computer Scientists 2014 Vol II, IMECS 2014, March 12 – 14.
[5] J.Sudhakar, A. Mallikarjuna Prasad, Ajit Kumar Panda, ―Behavior of Self Timed Null Convention Logic Circuits with Threshold Variations, International Journal of Emerging Trends in Engineering Research (IJETER), Vol. 3 No.6, Pages : 173- 179 (2015).
[6] Meng-Chou Chang, Ming-Hsun Hsieh, and Po-Hung Yang, ―Low-Power Asynchronous NCL Pipelines With Fine- Grain Power Gating and Early Sleep, IEEE transactions on circuits and systems—ii: express briefs, vol. 61, no. 12, december 2014.
[7] Mohammed Sohail Ahmed, B.Rajkumar, ―Design of Gate Mapping Automation for Asynchronous Null Convention Logic Circuits, International journal of scientific engineering and technology research, ISSN 2319-8885 Vol.03,Issue.47 December-2014, Pages:9620-9628.
[8] S.C. Smitha, R.F. DeMarab, J.S. Yuanb, ―Optimization of NULL convention self-timed circuits, INTEGRATION, the VLSI journal 37 (2004) 135–165,December 2003.
[9] Qingyu Ou, Fang Luo, Shilei Li, and Lu Chen, ―Circuit Level Defences Against Fault Attacks in Pipelined NCL Circuits IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 23, No. 9, September 2013.
[10] Sameh Andrawes and Paul Beckett, ―Ternary Circuits for Null Convention Logic, IEEE Trans.2011.