Null Convention Logic (NCL) Design of Efficient Sorting Unit

International Journal of Electronics and Communication Engineering

© 2017 by SSRG - IJECE Journal

Volume 4 Issue 12

Year of Publication : 2017

Authors : E. Juhi Gladies and E. Thanga selvi

10.14445/23488549/IJECE-V4I12P102

How to Cite?

E. Juhi Gladies and E. Thanga selvi, "Null Convention Logic (NCL) Design of Efficient Sorting Unit," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 12, pp. 4-7, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I12P102

Abstract:

 Sorting is a method through which the data is assembled in ascending or descending order. To construct a sorting unit of N values from M inputs. The basic OR, AND gate are used to construct a sorting unit. NCL threshold gates are a specialized case of the logical operands or gates. Self-timed logic design process are developed using Threshold Combinational Reduction (TCR) in the Null Convention Logic (NCL) paradigm. NCL logic functions are constructed using 27 distinct transistor built-up networks. To implement partial sorting using NCL and max-set-selection units with low delay units. But, higher-speed estimation usually raises power consumption extremely. To reduce that problem, a low-power, high-throughput, and modular design of partial sorting network is presented. This paper presents the NCL threshold logic has been used in sorting techniques. The proposed technique is used for lower power consumption and high operating speed. All the circuits in null conventional logic is developed using Threshold Combinational Reduction (TCR) method. Overall NCL logic techniques are meant for reduced area and delay of sorted output.

Keywords:

Null convention logic (NCL), Threshold combinational reduction (TCR),delay insensitive, sorting network, Multi threshold complementary metal oxide semiconductor (MTCMOS) ,Threshold gates.

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