Usage of Gain Cell Embedded Dram in Low Power Applications

International Journal of Electronics and Communication Engineering

© 2017 by SSRG - IJECE Journal

Volume 4 Issue 12

Year of Publication : 2017

Authors : P.Sujitha and M.Deivakani

10.14445/23488549/IJECE-V4I12P103

How to Cite?

P.Sujitha and M.Deivakani, "Usage of Gain Cell Embedded Dram in Low Power Applications," SSRG International Journal of Electronics and Communication Engineering, vol. 4,  no. 12, pp. 8-12, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I12P103

Abstract:

 Gain - Cell embedded DRAM (GC-DRAM) has latterly been confessed as conceivably replaced to conventional SRAM. While GC- e DRAM potentially allow for high -balance , low- outflow, low- voltage, and 2 - focussed verdict, its modest priority time permit occasional, power - hungry renew cycles. The disadvantages are further strengthen at ascend inventions, where expanding sub threshold leakage currents and decreased in - cell storage capacitances results in faster data deterioration. In this project, we present a novel 4T GC- e DRAM bit cell that utilizes an internal feedback contraption to remarkably increase the data retention time in scaled CMOS technologies. A 2 kb memory macro was implemented in a low power 65nm CMOS technology, displaying an over 3× improvement in retention time over the best previous publication at this node.

Keywords:

Gain-cell Embedded dynamic Random Access Memory (GC-e DRAM), Single Event Upset (SEU), Error Correction Codes (ECC), Data Retention Time, Low Power Applications.

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