Data Pattern Aware Error Prevention Technique: Survey
|International Journal of Electronics and Communication Engineering|
|© 2017 by SSRG - IJECE Journal|
|Volume 4 Issue 12|
|Year of Publication : 2017|
|Authors : M.Priyadharshini and T.Chelladurai|
How to Cite?
M.Priyadharshini and T.Chelladurai, "Data Pattern Aware Error Prevention Technique: Survey," SSRG International Journal of Electronics and Communication Engineering, vol. 4, no. 12, pp. 13-15, 2017. Crossref, https://doi.org/10.14445/23488549/IJECE-V4I12P104
This paper centers the diminishment system of Bit Error Rate(BER) caused in NAND flash recollections. Program aggravate, read irritate and maintenance time clamor are the significant reason for Bit Error Rate(BER) in multilevel cell(MLC) NAND flash memory. BER increments with program/erase(P/E) cycle and innovation scaling of NAND flash memory, which vigorously relies upon put away information design. The information trustworthiness is guaranteed utilizing error amendment code(ECC) and a Data Pattern Aware(DPA) to control the proportion of 0's and 1's in put away information to diminish the likelihood of information designs which are effortlessly influenced by gadget clamor are survived.
Flash memories, Bit error rate (BER), error correction code (ECC), data integrity..
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