Analysis of Low Power Consuming Adder using Microwind EDA Tool

International Journal of Electronics and Communication Engineering

© 2018 by SSRG - IJECE Journal

Volume 5 Issue 4

Year of Publication : 2018

Authors : Mrs.S.I.Padma, D.Emi Delphina, S.Renisha and K.Karthika

10.14445/23488549/IJECE-V5I4P101

How to Cite?

Mrs.S.I.Padma, D.Emi Delphina, S.Renisha and K.Karthika, "Analysis of Low Power Consuming Adder using Microwind EDA Tool," SSRG International Journal of Electronics and Communication Engineering, vol. 5,  no. 4, pp. 1-6, 2018. Crossref, https://doi.org/10.14445/23488549/IJECE-V5I4P101

Abstract:

Addition is one of the basic arithmetic operations. Low power adders are used to reduce the overall power consumption of micro-electronic systems. The role of adders are important in almost all filed .With the help of low power adders , all the other systems which make use of adders may dissipate less power. This project presents a detailed comparison between the full adders designed using gates and different styles of full adder designed using transistors. This project focus mainly on the comparisons among conventional CMOS adder, transmission gate adder, square root based adder, static energy recovery adder . All the simulation results are done using Digital Schematic editor (DSCH) and the functionality is verified using the layout editor tool, MICROWIND. The sole objective of this project to conclude with a better estimate and ease in selecting a low power consuming adders.

Keywords:

CMOSadder,lowPower,Microwind,transmission gate adder,SERF.

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