Design of Low Power Sense Amplifier Flip Flop using GDI and FinFET Techniques

International Journal of Electronics and Communication Engineering

© 2018 by SSRG - IJECE Journal

Volume 5 Issue 5

Year of Publication : 2018

Authors : M.Aruna devi and A.Jagadeeswaran

10.14445/23488549/IJECE-V5I5P102

How to Cite?

M.Aruna devi and A.Jagadeeswaran, "Design of Low Power Sense Amplifier Flip Flop using GDI and FinFET Techniques," SSRG International Journal of Electronics and Communication Engineering, vol. 5,  no. 5, pp. 4-10, 2018. Crossref, https://doi.org/10.14445/23488549/IJECE-V5I5P102

Abstract:

This proposal is based on the analysis of basic memory elements called flip-flops. In order to achieve a design that is both highly efficient and high performance, it is necessary to take care while designing these memory elements i.e. flip-flops and latches. The proposed technique enhanced with new SAFF using GDI technique in which GDI latch has been used. The proposed method is designed with dual gate FinFET device to improve performance of this device which is most frequency used in memory devices. FinFET is a promising alternative to conventional MOSFET - which has reached its limits and has too much leakage for too little performance gain. FinFET is being recommended as the basis for future IC processes because of its power/performance benefits, scalability, superior controls over short channel effects etc.The FinFET based circuits provides better results in switching activity when compare with conventional CMOS technology. It results power efficient circuits. The new flip-flop uses a new output stage latch topology using GDI technique that significantly reduces power consumption and has improved power-delay product (PDP). In circuit implementation, transistor sizes are optimized with respect to the power delay product (PDP). The simulation results shows that the proposed method is more efficient than the conventional circuits, while considering the parameters like PDP, average power consumption, and leakage power consumption. Simulations are carried out by TANNER EDA(T-SPICE)<-SPICE and finally the power comparison is done with various flip flops.

Keywords:

Flip-flop, GDI, FinFET, Low Power.

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