Design of SRAM based BTI Sensor for Improved Cell Stability

International Journal of Electronics and Communication Engineering

© 2018 by SSRG - IJECE Journal

Volume 5 Issue 8

Year of Publication : 2018

Authors : Y.Alekhya, T.Sindhusha, S.S.Mahalakshmi, N.Swathi and S.V.Sharvani

10.14445/23488549/IJECE-V5I8P102

How to Cite?

Y.Alekhya, T.Sindhusha, S.S.Mahalakshmi, N.Swathi and S.V.Sharvani, "Design of SRAM based BTI Sensor for Improved Cell Stability," SSRG International Journal of Electronics and Communication Engineering, vol. 5,  no. 8, pp. 5-13, 2018. Crossref, https://doi.org/10.14445/23488549/IJECE-V5I8P102

Abstract:

The semiconductor industry has reached its focal point with exceptional hike and success in integrated circuit (IC) manufacturing. Due to technology scaling a major reliability issue exists which is time dependent degradation-bias temperature instability (BTI). The parametric variations-PVT (Power, supply Voltage, Temperature) lead to degradation of System-on-chip (SOC’s) performance thus increasing the delay over long periods. An aging sensor is thus proposed, for CMOS memories in particular for SRAM cells, to detect the delay faults by active monitoring. The performance of sensor is achieved by tracking the bit line transitions and the output is set high for slow transitions i.e., if transitions didn’t occur in expected time frame. The sensors’ operation is demonstrated in MENTOR GRAPHICS simulations using 35nm technology.

Keywords:

 Aging sensor, CMOS memories, slow transitions.

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