6T FA Using 2T EX-OR Gate

International Journal of Electronics and Communication Engineering
© 2018 by SSRG - IJECE Journal
Volume 5 Issue 9
Year of Publication : 2018
Authors : M.Sai Lakshmi, K.Mahammad Haneef, T.V.Nirmala, Dr.T.Lalith Kumar and S.Saleem
How to Cite?

M.Sai Lakshmi, K.Mahammad Haneef, T.V.Nirmala, Dr.T.Lalith Kumar and S.Saleem, "6T FA Using 2T EX-OR Gate," SSRG International Journal of Electronics and Communication Engineering, vol. 5,  no. 9, pp. 16-19, 2018. Crossref, https://doi.org/10.14445/23488549/IJECE-V5I9P104


 EX-OR gate plays a major role in digital circuits. This paper presents the 6-transistors FA with a 2-T EXOR gate. In these design we using few transistor and it does not uses the additional complementary input signal. By decreasing the transistor count in a FA circuit, we can able to decrease the area, expenditure of the power and delay. The proposed 6 Transistor FA has been contrast with the earlier 38T,28T,14T,10TFAs.


 6-T FA, area, delay, 2-T EX-OR gate.


[1] Bui H.T, Al-Sheraidah A.K and Wang Y, New 4-transistors XOR and XNOR designs, in Proc. 2nd IEEE Asia Pacific Conference, ASIC, 2000, 25–28. 
[2] Bui H.T, Wang Y and Jiang Y, Design and analysis of low-power 10-transistor full adders using XOR-XNOR gates,IEEE Transactions Circuits Systems II, Analog Digital Signal Process, 49 (1), 2002, 25– 30. 
[3] Bui H.T, Wang Y, Jiang Y, Design and analysis of10-transistor full adders using novel XOR–XNOR gates, in Proc, 5th International Conference on Signal Process, 1, 2000, 619–622. 
[4] Jin-Fa Lin Hwang Y.T, Sheu M.H and Ho C.C, A Novel High-Speed and Energy Efficient10-Transistor Full Adder Design, IEEE Transactions on Circuits and Systems, 54 (5), 2007, 1050-1059. 
[5] Kaarthik K and Vivek C, Hybrid Han Carlson Adder Architecture for Reducing Power and Delay, Middle-East J. Sci. Res, 24(Special Issue on Innovations in Information, Embedded and Communication Systems), 2016, 308-313. 
[6] Kavitha V, Palanisamy V, New Burst Assembly and Scheduling T technique for Optical Burst Switching Networks, Journal of Computer Science, 9 (8), 2013, 1030-1040. 
[7] Kavitha V, Palanisamy V, Simultaneous Multi-path Transmission for Burst Loss Recovery in Optical Burst SwitchingNetworks, European Journal of Scientific Research, 87 (3), 2012, 412-416. 
[8] Leblebici Y, Kang S.M, CMOS Digital Integrated Circuits, Singapore, McGraw Hill, 2nd edition,1999. 
[9] PalanivelRajan S, Experimental Explorations on EOG Signal Processing for Real Time Applications in Lab VIEW,IEEE Digital Library Xplore, 2012. 
[10] PalanivelRajan S, Poovizhi M, Design of Patch Antenna Array for Radar Communication, Journal of Chemical and Pharmaceutical Sciences, Special Issue, 8, 2016, 38-40. 
[11] Radhakrishnan D, Low-voltage low-power CMOS full adder, in Proc, IEEE Circuits Devices System, 148, 2001, 19-24. 
[12] Shams A.M, Darwish T.K and Bayoumi M.A, Performance analysis of low-power 1-bit CMOS full adder cells, IEEE Trans, Very Large Scale Integration (VLSI) Systems, 10 (1), 2002.