Design and Implementation of 16-Bit Baugh-Wooley Multiplier

International Journal of Electronics and Communication Engineering

© 2018 by SSRG - IJECE Journal

Volume 5 Issue 12

Year of Publication : 2018

Authors : B.Maha Lakshmi and M.Bhavani

10.14445/23488549/IJECE-V5I12P101

How to Cite?

B.Maha Lakshmi and M.Bhavani, "Design and Implementation of 16-Bit Baugh-Wooley Multiplier," SSRG International Journal of Electronics and Communication Engineering, vol. 5,  no. 12, pp. 1-5, 2018. Crossref, https://doi.org/10.14445/23488549/IJECE-V5I12P101

Abstract:

In this paper we centered upon the Design and Implementation of 16-bit Baugh-Wooley multiplier . Different electronic gadgets dependent on VLSI innovation have been important to the examination network from a very long while. These incorporate plans for adders and multipliers. This postulation focuses on a multiplication of marked number with two's complement shape, in particular the Baugh-Wooley multiplier and the device for this reason for existing was Xilinx ISE 14.2. The Baugh-Wooley multiplier with its fundamental writing survey and its Mathematical figuring for 16-bit multiplier was given reference to 4-bit engineering as in writing. It very well may be seen that the circuit comprises fundamentally of a few full-adders so a decent full-adder arrangement in Verilog-HDL straightforwardly adds to the productivity of the Baugh-Wooley multiplier. In this way the full-adder can be acknowledged in Xilinx ISE 14.2. At long last we plan in Xilinx and investigate the simulated result . The plan was observed to be proficient than the current structure of multiplier for two's complement numbers.

Keywords:

Baugh-Wooley Multiplier ,Fulladder, VLSI, Xilinx.

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