Optimized Design of Low Power and High Speed Ring Counter

International Journal of Electronics and Communication Engineering

© 2019 by SSRG - IJECE Journal

Volume 6 Issue 2

Year of Publication : 2019

Authors : Namrata Joshi, Ravi Kumar Jangir

10.14445/23488549/IJECE-V6I2P101

How to Cite?

Namrata Joshi, Ravi Kumar Jangir, "Optimized Design of Low Power and High Speed Ring Counter," SSRG International Journal of Electronics and Communication Engineering, vol. 6,  no. 2, pp. 1-4, 2019. Crossref, https://doi.org/10.14445/23488549/IJECE-V6I2P101

Abstract:

Sequential circuits have an important role in designing the digital system. As VLSI technologies’ growth increases day by day, the main concern for researchers is to implement low power and high-speed sequential circuit with downscaling of chip size. The counter is a basic element to design many applications like timing circuits, memories, frequency synthesizer, and processor. In this paper, the implementation of the 4-bit Ring counter has been done using BICMOS logic. Bipolar and CMOS transistors are combined to make this logic to get advantages of both the logics. Cadence Virtuoso schematic editor and Cadence Virtuoso analog design environment have been used to design the proposed counter’s schematic circuit and for the simulation process, respectively. Calculation of power dissipation and delay has been performed for the proposed counter circuit, which is 214.45pw of power dissipation and 73.96ps of delay, then compared these results with previously designed counter circuit results. Performance analysis has been done based on this comparison by which we can conclude that the proposed counter circuit has low power dissipation and high speed compared to prior implemented counter circuits.

Keywords:

BICMOS, Master-Slave D flip flop, Latch-up, Cadence, Ring counter.

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