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Implementation of Full -Parallelism AES Encryption and Decryption

International Journal of Electronics and Communication Engineering
© 2014 by SSRG - IJECE Journal
Volume 1 Issue 8
Year of Publication : 2014
Authors : M.Anto Merline
10.14445/23488549/IJECE-V1I8P103
pdf
How to Cite?

M.Anto Merline, "Implementation of Full -Parallelism AES Encryption and Decryption," SSRG International Journal of Electronics and Communication Engineering, vol. 1,  no. 8, pp. 1-5, 2014. Crossref, https://doi.org/10.14445/23488549/IJECE-V1I8P103

Abstract:

-Advanced Encryption Standard (AES) is a symmetric key encryption algorithm used to encrypt block of data. AES is widely used encryption standard in today’s world. In this paper inorder to increase the performance of the encryption algorithm, various architecture models is proposed with data-level parallelism and task-level parallelism. The proposed architecture is design in ASAP processor. The proposed architecture increases the throughput and speed of the encryption and decryption process by reducing the latency between the processes by using parallelism architecture. This paper proposed four different architecture models among that full parallelism architecture gives better performance among other models. The throughput of this model is 70 cycles per block. The encryption process uses online key expansion which increases the security of the data. The full parallelism gives higher throughput per chip area compare to other existing techniques.

Keywords:

symmetric key, data level parallelism, task level parallelism, online Key Expansion, ASAP.

References:

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[2] NIST, “Advanced Encryption Standard (AES),” http://csrc.nist.-gov/publications/fips/fips197/fips-197.pdf, Nov. 2001.
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