Different parameter analysis for SRAM

International Journal of Electronics and Communication Engineering

© 2019 by SSRG - IJECE Journal

Volume 6 Issue 12

Year of Publication : 2019

Authors : Vartika Pandey, Manisha Pattaniak, R K Tiwari

10.14445/23488549/IJECE-V6I12P102

How to Cite?

Vartika Pandey, Manisha Pattaniak, R K Tiwari, "Different parameter analysis for SRAM," SSRG International Journal of Electronics and Communication Engineering, vol. 6,  no. 12, pp. 3-8, 2019. Crossref, https://doi.org/10.14445/23488549/IJECE-V6I12P102

Abstract:

In today’s VLSI design circumstances, upscaling of technology and downscaling of transistors are inversely proportional. Power dissipation impactsSRAM cells widely as the technology shrinks down. Static Random Access Memory (SRAM) is designed to interface with CPU directly, DSP processors, μprocessors, and low-power applications such as handheld devices with long battery life. In the total power consumption, leakage and other parameters also play an important role in the circuit’s performance. In this paper, we have applied two diverse technologies on 6 T SRAM, and the result has been comparedwith6T SRAM formed with memristor.

Keywords:

SRAM, DTMOS, Memristor, Sleep transistor

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