Physical Design Implementation of Openmsp430 Using Different Approaches
|International Journal of Electronics and Communication Engineering|
|© 2020 by SSRG - IJECE Journal|
|Volume 7 Issue 5|
|Year of Publication : 2020|
|Authors : Nagella Jyothsna, Dr.T.Lalith kumar|
How to Cite?
Nagella Jyothsna, Dr.T.Lalith kumar, "Physical Design Implementation of Openmsp430 Using Different Approaches," SSRG International Journal of Electronics and Communication Engineering, vol. 7, no. 5, pp. 56-58, 2020. Crossref, https://doi.org/10.14445/23488549/IJECE-V7I5P109
Due to rapid growth in electronics and communication engineering, VLSI plays an essential role in the mechanization of distinct steps about the design and forgery of the VLSI chips. In this paper, we appraised the openMSP430 module in which lower technologies such as 45nm, 180nm, 350nm, and 500nm are investigated from RTL to GDSII. The design's core area is being considered up to 0.7 with high accomplishment, with the concern of clock frequency 404.85 MHZ with a significant reduction of 3440736 μm2 die area. Primarily the design is being optimized for 500nm net-list, later it has been carried over lower technologies (350nm, 180nm, 45nm) with the enhancement of PPA (performance, power, and area) are improved as scheme towards lower strategies by open source tools such as the proton, open STA and Q-flow
Synthesis; floor-planning; placement; physical design, routing
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