A Review of Leakage Power Reduction Techniques for VLSI Applications

International Journal of Electronics and Communication Engineering

© 2021 by SSRG - IJECE Journal

Volume 8 Issue 2

Year of Publication : 2021

Authors : Shruti Hathwalia, Dr.Naresh Grover

10.14445/23488549/IJECE-V8I2P101

How to Cite?

Shruti Hathwalia, Dr.Naresh Grover, "A Review of Leakage Power Reduction Techniques for VLSI Applications," SSRG International Journal of Electronics and Communication Engineering, vol. 8,  no. 2, pp. 1-5, 2021. Crossref, https://doi.org/10.14445/23488549/IJECE-V8I2P101

Abstract:

Power dissipation has become one of the VLSI circuit structure's significant worries with the fast launching of battery worked applications. In high-performance structures, the leakage segments of power consumption are equivalent to the switching segment. This will keep incrementing with innovation scaling, except if effective procedures are introduced for controlling the leakage. This paper gives a thorough report, examination, and correlation of leakage power reduction systems and techniques. Additionally, the advantages and disadvantages of different strategies for decreasing leakage power are introduced. These methods can be stretched out to any complex advanced digital implementation.

Keywords:

Leakage/ Spillage Power reduction, CMOS circuits, Leakage/Spillage current, MTCMOS

References:

[1] Pramoda N V et al.,Analysis and Comparison of Methods to reduce leakage power and latency to improve performance of VLSI circuits, Asian Journal of Convergence in Technology, 3(2).
[2] M.Geetha Priya et al. "Leakage Power Reduction Techniques in Deep Submicron Technologies for VLSI Applications." International Conference on Communication Technology and System Design,(2012) 1163-1170.
[3] Sangeetha Parshionkar et al., Leakage Power using Multi Threshold Voltage CMOS Technique, International Journal of Scientific & Engineering Research, 4(10)(2013).
[4] Bipin Gupta, Sangeeta Nakhate.,TRANSISTOR GATING: A Technique for Leakage Power Reduction in CMOS Circuits, International Journal of Engineering Technology and Advanced Engineering, (2012).
[5] A.Abdollahi, F.Fallah, and M.Pedram., Leakage current reduction in CMOS VLSI circuits by input vector control, IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, 12, (2)(2004) 140-154.
[6] Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Leakage Current Mechanisms in Deep-Submicrometer CMOS Circuits: The IEEE.,2(2003).
[7] Wei. L, et al., Design and Optimization of Low Voltage High-Performance Dual Threshold CMOS Circuits, Proceedings of the 35th Design Conference (DAC), (1998) 489-494.
[8] Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., and Yamada, J., 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, IEEE Journal of Solid-State Circuits 30,(1995) 847-854.
[9] Kawaguchi, H., Nose, K., and Sakurai, T., A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Pico ampere Stand-By Current, IEEE Journal of Solid-State Circuits 35(10)(2000) 1498-1501.
[10] Siva Narendran, Shekhar. Borkar, Vivek De, Dimitri Antoniadisn, and Anantha Chandrakasann, Scaling of Stack Effect and its Application for Leakage Reduction, in Proc. ISLPED, (2001) 195-200.
[11] Park, J. C., and Mooney III, V. J.,Sleepy Stack Leakage Reduction, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 14, (2006) 1250-1263.
[12] S. Kim and V. Mooney, The Sleepy Keeper Approach: Methodology, Layout and Power Results for a 4 bit Adder, Technical Report GITCERCS-06-03, Georgia Institute of Technology, March 2006, http://www.cercs.gatech.edu/tech-reports/tr2006/git-cercs-06-03.pdf.