Study of Hot Carrier Degradation in N-Channel LDMOS Transistor Under Thermal Stress

International Journal of Electronics and Communication Engineering

© 2022 by SSRG - IJECE Journal

Volume 9 Issue 5

Year of Publication : 2022

Authors : Mohamed Ali Belaid

10.14445/23488549/IJECE-V9I5P102

How to Cite?

Mohamed Ali Belaid, "Study of Hot Carrier Degradation in N-Channel LDMOS Transistor Under Thermal Stress," SSRG International Journal of Electronics and Communication Engineering, vol. 9,  no. 5, pp. 8-16, 2022. Crossref, https://doi.org/10.14445/23488549/IJECE-V9I5P102

Abstract:

Thermal constraints, special in high-temperature levels, are the majority detected degradation phenomenon in Radio Frequency power devices. To assess the shift level, the focal sign results from the on-state resistor (RDSON) methodically related to the internal device structure evolution. This evaluates thermal constraints properties on currentvoltage behaviors of power RF N-LDMOS components, particularly of the RDSON. The resistor parameter, a principal restriction of the N-channel LDMOS components in the greatest temperature procedures, can partly or entirely modify the reliability of the physical and electrical components. RDS-on is highly dependent on temperature. The measurement characteristics significant to the thermal evaluation behavior of the component are described and confirmed through the elementary physical performance. The experimental results investigation is presented and used to study the physical aspect of temperature effects on N-channel LDMOS reliability. Physical quantities such as current lines, concentration, and mobility are considered depending on the temperature reliance. To finish, the study of the initial effects is presented and discussed.

Keywords:

Reliability, Characterization, LDMOS, Temperature effects, Hot carrier phenomenon.

References:

[1] Parthasarathy Nayak, Sumit Kumar Pramanick, and Kaushik Rajashekara, “A High-Temperature Gate Driver for Silicon Carbide MOSFET,” IEEE Transactions on Industrial Electronics, vol. 65, pp. 1955-1964, 2018. Crossref, http://doi.org/10.1109/TIE.2017.2745465
[2] M.A. Belaïd et al., “Analysis and Simulation of Self-Heating Effects on RF LDMOS Devices,” Proceedings on IEEE Conference Simulation of Semiconductor Processes and Devices, SISPAD, Tokyo, Japan, pp. 231-234, 2005. Crossref, http://doi.org/10.1109/SISPAD.2005.201515
[3] Mohamed Ali Belaïd, “Symptom Reliability: S-Parameters Evaluation of Power MOSFET After Pulsed-RF Life Tests for a Radar Application,” IET Circuits Devices System, vol. 12, no. 5, pp. 571-578, 2018. Crossref, https://doi.org/10.1049/iet-cds.2018.0005
[4] Product News from Philips Semiconductors, LDMOS Devices to Boost Base Station Efficiency, 2003.
[5] Pedro J. Escalona-Cruz, Manuel A. Jimenez-Cedeño, and Rogelio Palomera-García, “Automated RDSon Characterization for Power MOSFETS,” IEEE Conference Latin American Symposium on Circuits & Systems (LASCAS), Montetevideo, Uruguay, pp. 1-4, 2015. Crossref, https://doi.org/10.1109/LASCAS.2015.7250483
[6] Nasser Badawi et al., “Investigation of the Dynamic on-State Resistance of 600 V Normally-off and Normally-on GaN HEMTs,” IEEE Transactions on Industry Applications, vol. 52, no. 6, pp. 4955-4964, 2016. Crossref, https://doi.org/10.1109/TIA.2016.2585564
[7] Mehdi Saremi et al., “SOI LDMOSFET with Up and Down Extended Stepped Drift Region,” Journal of Electronic Materials, vol. 46, pp. 5570-5576, 2017. Crossref, https://doi.org/10.1007/s11664-017-5645-z
[8] Ali A. Orouji, S.E. Jamali Mahabadi, and P. Keshavarzi, “A Novel Partial SOI LDMOSFET with a Trench and Buried P Layer for Breakdown Voltage Improvement,” Superlattices and Microstructures, vol. 50, no. 5, pp. 449-460, 2011. Crossref, https://doi.org/10.1016/j.spmi.2011.07.013
[9] Li-Sheng Wang et al., “Influences of Remote Coulomb and Interface-Roughness Scatterings on Electron Mobility of InGaAs nMOSFET With High-k Stacked Gate Dielectric,” IEEE Transactions on Nanotechnology, pp. 854-861, 2015. Crossref, https://doi.org/10.1109/TNANO.2015.2451134
[10] I. Cortes et al., “Analysis of Hot-Carrier Degradation in a SOI LDMOS Transistor with a Steep Retrograde Drift Doping Profile,” Elsevier Microelectronics Reliability, vol. 45, no. 3-4, pp. 493-498, 2004. Crossref, https://doi.org/10.1016/j.microrel.2004.08.005
[11] Ph. Kouakou, “Physical Study of Nonlinearities in Radio Frequency MOS Transistors,” PhD Thesis, University Paul Sabatier of Toulouse, 1999. 
[12] Ying Cai et al., “Optimization of RF Performance and Reliability of 28V RF-LDMOS,” IEEE Conference China Semiconductor Technology International Conference, CSTIC 2019, Shanghai, China, pp. 1-3, 2019. Crossref, https://doi.org/10.1109/CSTIC.2019.8755763
[13] G. Groesenken et al., “The Temperature Dependence of Threshold Voltage in Thin-Film SO1 MOSFET’s,” IEEE Electron Device Letters, vol. 11, no. 8, pp. 329-331, 1990. Crossref, https://doi.org/10.1109/55.57923
[14] M. Miller, T. Dinh, and E. Shumate, “A New Empirical Large-Signal Model for Silicon RF LDMOSFET’s,” IEEE MTT-S Technology Wireless Application, Dig, pp. 19-22, 1997.
[15] M.A. Belaïd et al., “Reliability Study of Power RF LDMOS Device Under Thermal Stress,” Microelectronics Journal, vol. 38, no. 2, pp. 164-170, 2006. Crossref, https://doi.org/10.1016/j.mejo.2006.08.004
[16] Siyang Liu et al., “Lateral DMOS with Partial-Resist-Implanted Drift Region for Alleviating Hot-carrier Effect,” IEEE Transactions on Device and Materials Reliability, vol. 99, pp. 780-784, 2017. Crossref, https://doi.org/10.1109/TDMR.2017.2765687
[17] Chien-Yu Lin et al., “Analysis of Contrasting Degradation Behaviors in Channel and Drift Regions Under Hot Carrier Stress in PDSOI LD N-Channel MOSFETs,” IEEE Electron Device Letters, vol. 38, no. 6, pp. 705-707, 2017. Crossref, https://doi.org/10.1109/LED.2017.2694972
[18] Mohamed Ali Belaid, “Temperature Effects in a Power RF LDMOS Device Performance Due to Hot Carrier,” SSRG International Journal of Electrical and Electronics Engineering, vol. 94, pp. 1-6, 2022. Crossref, https://doi.org/10.14445/23488379/IJEEE-V9I4P10