Reliability Evaluation of NLDMOS Transistor Based on Advanced Aging Test Including Hot Carrier Phenomenon

International Journal of Electronics and Communication Engineering

© 2022 by SSRG - IJECE Journal

Volume 9 Issue 8

Year of Publication : 2022

Authors : Mohamed Ali Belaid

10.14445/23488549/IJECE-V9I8P101

How to Cite?

Mohamed Ali Belaid, "Reliability Evaluation of NLDMOS Transistor Based on Advanced Aging Test Including Hot Carrier Phenomenon," SSRG International Journal of Electronics and Communication Engineering, vol. 9,  no. 8, pp. 1-7, 2022. Crossref, https://doi.org/10.14445/23488549/IJECE-V9I8P101

Abstract:

This manuscript treats the relative performance analysis of the hot carrier persuaded electrical behavior failure in RF power NLDMOS components afterwards innovative procedures of accelerated aging tests under various conditions (electrical and thermal stress). The results show the performances shift for critical electrical parameters such as the Miller Crss capacitance and the Cgd gate-drain capacitance under various aging tests. To understand the parameter shift that appears during aging, we used a new electro-thermal perfect model executed by Agilent’s Advanced Design System (ADS) software as a reliability tool beneath form SDD, meaning Symbolic Defined Device, also with a physical numerical simulation (2D Silvaco-Atlas software) to prove qualitatively degradation phenomena, which are resulted through the generation of interface state also stuck electrons, then outcomes in a buildup at Si/SiO2 border of negative charge.

Keywords:

Reliability, Characterization, LDMOS, Thermal effects, Hot carrier phenomenon.

References:

[1] Shaohua Zhou, and Jian Wang, “An Rf Stress-Based Thermal Shock Test Method for a CMOS Power Amplifier,” Electron Devices Society, vol. 9, pp. 1024-1029, 2021. Crossref, https://doi.org/10.1109/JEDS.2021.3121132
[2] Parthasarathy Nayak et al., “A High Temperature Gate Driver for Silicon Carbide Mosfet,” IEEE Transactions on Industrial Electronics, vol. 65, no. 3, pp. 1955–1964, 2018. Crossref, https://doi.org/10.1109/TIE.2017.2745465
[3] M.A. Belaïd et al., “Analysis and Simulation of Self-Heating Effects on RfLdmos Devices,” Proceedings of IEEE Conference Simulation of Semiconductor Processes and Devices, pp. 231–234, 2005. Crossref, https://doi.org/10.1109/SISPAD.2005.201515
[4] Kun-Ming Chen et al., “Characterization and Modelling of SOI Varactors at Various Temperatures,” IEEE Transactions on Electron Devices, vol. 51, no. 3, pp. 427-433, 2004. Crossref, https://doi.org/10.1109/TED.2003.822585
[5] Mohamed Ali Belaïd, “Symptom Reliability: S-Parameters Evaluation of Power MosfetAfter Pulsed-Rf Life Tests for a Radar Application,” IET Circuits Devices System, vol. 12, no. 5, pp. 571-578, 2018. Crossref, https://doi.org/10.1049/iet-cds.2018.0005
[6] Product News From Philips Semiconductors, “LDMOS Devices to Boost Base Station Efficiency,” 2003. 
[7] Pedro J. Escalona-Cruz, Manuel A. Jimenez-Cedeno, and Rogelio Palomera-García, “Automated Rdson Characterization for Power Mosfets,” IEEE Conference, Latin American Symposium on Circuits & Systems LASCAS, pp. 1-4, 2015. Crossref, https://doi.org/10.1109/LASCAS.2015.7250483
[8] Nasser Badawi et al., “Investigation of the Dynamic on-State Resistance of 600 V Normally-Off and Normally-on GanHemts,” IEEE Transactions on Industry Applications, vol. 52, no. 6, pp. 4955-4964, 2016. Crossref, https://doi.org/10.1109/TIA.2016.2585564
[9] M. Saremi et al., “SoiLdmosfet with Up and Down Extended Stepped Drift Region,” Journal of Electronic Materials, vol. 46, pp. 5570- 5576, 2017.
[10] Ali A. Orouji, S.E. Jamali Mahabadi, and P. Keshavarzi, “A Novel Partial SoiLdmosfet with a Trench and Buried P Layer for Breakdown Voltage Improvement,” Microelectronic Reliability, vol. 50, no. 5, pp. 449-460, 2011. Crossref, https://doi.org/10.1016/j.spmi.2011.07.013
[11] Li-Sheng Wang et al., “Influences of Remote Coulomb and Interface-Roughness Scatterings on Electron Mobility of IngaasNmosfet with High-K Stacked Gate Dielectric,” IEEE Transactions on Nanotechnology, vol. 14, no. 5, pp. 854–861, 2015. Crossref, https://doi.org/10.1109/TNANO.2015.2451134
[12] I. Cortes et al., "Analysis of Hot-Carrier Degradation in a SoiLdmos Transistor with a Steep Retrograde Drift Doping Profile," Elsevier Microelectronics Reliability, vol. 45, pp. 493-498, 2005. [
13] M.A. Belaïd et al., “2-D Simulation and Analysis of Temperature Effects on Electrical Parameters Degradation of Power RF LDMOS Device,” Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, vol. 253, no. 1-2, pp. 250–254, 2006. Crossref, https://doi.org/10.1016/j.nimb.2006.10.040
[14] Ph. Kouakou, "Physical Study of Nonlinearities in Radio Frequency MOS Transistors," PhD Thesis, University Paul Sabatier of Toulouse, 1999.
[15] C. Ying et al., “Optimization of RF Performance and Reliability of 28v RF-LDMOS,” IEEE Conference China Semiconductor Technology International Conference, pp. 19-23, 2019. Crossref, https://doi.org/10.1109/CSTIC.2019.8755763
[16] G. Groesenken et al., “Temperature Dependence of Threshold Voltage in Thin-Film SO1 MOSFET’s,” IEEE Electron Device Letters, vol. 11, no. 8, pp. 329-332, 1990. Crossref, https://doi.org/10.1109/55.57923
[17] M. Miller, T. Dinh, and E. Shumate, “A New Empirical Large Signal Model for Silicon RF LDMOS FET’s,” IEEE MTT-S Technology Wireless Application Digest, pp. 19-22, 1997.
[18] M.A. Belaïd et al., "Reliability Study of Power RfLdmos Device Under Thermal Stress," Microelectrical Journal, vol. 38, no. 2, pp. 164–170, 2007. Crossref, https://doi.org/10.1109/55.57923
[19] Siyang Liu et al., “Lateral Dmos with Partial-Resist-Implanted Drift Region for Alleviating Hot-Carrier Effect,” IEEE Transactions on Device and Materials Reliability, vol. 17, no. 4, pp. 780-784, 2017. Crossref, https://doi.org/10.1109/TDMR.2017.2765687
[20] Chien-Yu Lin et al., “Analysis of Contrasting Degradation Behaviors in Channel and Drift Regions Under Hot Carrier Stress in PDSOILD N-Channel MOSFETs,” IEEE Electron Device Letters, vol. 38, no. 6, pp. 705-707, 2017. Crossref, https://doi.org/10.1109/LED.2017.2694972
[21] Takahiro Iizuka et al., “Validation on Duality in Impact-Ionization Carrier Generation at the Onset of Snapback in Power MOSFETs,” IEEE Conference ISDCS 2019, pp. 516-520. Crossref, https://doi.org/10.1109/ISDCS.2019.8719088