Radiation Tolerant PLL for Onboard FPGAs

International Journal of Electronics and Communication Engineering

© 2023 by SSRG - IJECE Journal

Volume 10 Issue 4

Year of Publication : 2023

Authors : Sourabh Kumar Jain, Usha Mehta, Mohit Sharma, Aarushi Bhandari, Kamal Poddar, Sanjay Trivedi

10.14445/23488549/IJECE-V10I4P106

How to Cite?

Sourabh Kumar Jain, Usha Mehta, Mohit Sharma, Aarushi Bhandari, Kamal Poddar, Sanjay Trivedi, "Radiation Tolerant PLL for Onboard FPGAs," SSRG International Journal of Electronics and Communication Engineering, vol. 10,  no. 4, pp. 51-62, 2023. Crossref, https://doi.org/10.14445/23488549/IJECE-V10I4P106

Abstract:

This paper proposes Fault Detection Isolation and Recovery (FDIR) techniques for in-built hard IPs of Phase Locked Loop (PLL) or Digital Clock Manager (DCM) of Field Programmable Gate Array (FPGA). PLLs inside the FPGAs are susceptible to Single Event Effects (SEE) even for space-qualified FPGAs. Under the radiation environment, loss of lock, perturbation in the clocks or no clocks are the common phenomena observed. Thus, we developed an Intellectual Property (IP) core based on FDIR, which adds redundancy to the PLL output and improves the Mean Time to Failures (MTTF). The generic IP core is technology independent and can be configured in dual or triple use of PLL mode. All the PLLs are kept as hot redundant mode, and their health is continuously monitored. SEE-affected PLL is immediately isolated, and the output is switched to a healthy PLL (if required) with or without a few cycle gaps. Recovery of faulty PLL is carried out in parallel. Telemetry signals notify every PLL switching and reset. For triple redundant PLL, minimum switching is ensured by logic. Redundancy bypass and selection of PLL make it work in case of complete failure of one or two PLL.

Keywords:

Clock multiplexing, DMR, FDIR, FPGA, PLL, Radiation tolerant, SEE, SEU, TMR.

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