Implementation of A DRAM 4×4 (Dynamic Random Access Memory) With Self Controllable Voltage Level (SVL) Technique

International Journal of Electronics and Communication Engineering

© 2014 by SSRG - IJECE Journal

Volume 1 Issue 10

Year of Publication : 2014

Authors : S Md Sameer and K Sanjeeva Rao

10.14445/23488549/IJECE-V1I10P108

How to Cite?

S Md Sameer and K Sanjeeva Rao, "Implementation of A DRAM 4×4 (Dynamic Random Access Memory) With Self Controllable Voltage Level (SVL) Technique," SSRG International Journal of Electronics and Communication Engineering, vol. 1,  no. 10, pp. 23-27, 2014. Crossref, https://doi.org/10.14445/23488549/IJECE-V1I10P108

Abstract:

Today trend is circuit characterized by responsibility, low power dissipation, low discharge current, low price and there's needed to scale back every of those. to scale back device size and increasing chip density have increase the planning quality. The recollections have provided the system designer with elements of right smart capability and in depth application. Dynamic random access memory (DRAM) offers the advantage for high-density knowledge storage. DRAM essentially a memory array with individual bit access refers to memory with each browse and Write capabilities. Here 3T DRAM is implementing with self manageable voltage level (svl) technique is for reducing discharge current in zero.12um technology. The simulation is completed by victimization micro wind three.1 & dsch2 and offers the advantage of reducing the discharge current up to fifty seven.

Keywords:

low leakage power, high performance, self controllable voltage level technique, low cost, low power.

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