Design and Implementation of 64-bit Multiplication using CLAA & CLSA

International Journal of Electronics and Communication Engineering

© 2014 by SSRG - IJECE Journal

Volume 1 Issue 10

Year of Publication : 2014

Authors : Shaik Mohammed IrshadAhmed and K. Sanjeeva Rao

10.14445/23488549/IJECE-V1I10P109

How to Cite?

Shaik Mohammed IrshadAhmed and K. Sanjeeva Rao, "Design and Implementation of 64-bit Multiplication using CLAA & CLSA," SSRG International Journal of Electronics and Communication Engineering, vol. 1,  no. 10, pp. 28-32, 2014. Crossref, https://doi.org/10.14445/23488549/IJECE-V1I10P109

Abstract:

In this paper deals with the comparison of the VLSI style of the carry lookahead adder (CLAA) based mostly} 32-bit signed and unsigned whole number number and also the VLSI style of the carry choose adder (CSLA) based 32-bit signed and unsigned whole number number. Multiplication could be a elementary operation in most signal process algorithms. Multipliers have giant space, long latency and consume hefty power. so low-power number style has been a vital half in low- power VLSI system style. A system’s performance is mostly determined by the performance of the number as a result of the number is mostly the slowest part within the system. moreover, it's usually the foremost space intense. Hence, optimizing the speed and space of the number could be a major style issue. Carry choose adder is one among the quickest adders utilized in several applications to perform quick arithmetic functions. This work evaluates the performance of the planned styles in terms of delay, speed(frequency)and memory. The CLAA based mostly} number uses the delay time of 99ns for activity multiplication operation wherever as in CSLA based number conjointly uses nearly identical delay time for multiplication operation. however the realm required for CLAA number is reduced to thirty one procurable the CSLA primarily based number to completethe multiplication operation

Keywords:

CLAA, CSLA, Delay, Area, Array Multiplier

References:

[1] Ramkumar, B. and Harish M Kittur,( 2012) “Low Power and Area Efficient Carry Select Adder”,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1-5.
[2] V.Vijayalakshmil, R.Seshadd, Dr.S.Ramakrishnan, (2013) Design and Implementation of 32 BitUnsigned Multiplier Using CLAA and CSLA 978-1-4673-5301-IEEE.
[3] P. Asadi and K. Navi, "A novel highs-speed 54-54 bit multiplier",Am. J Applied Sci., vol. 4 (9), pp. 666-672. 2007.
[4] W. Stallings, Computer Organization and Architecture Designing forPeljormance, 71h ed., Prentice Hall, Pearson Education International,USA, 2006, ISBN: 0-13-185644-8.
[5] F. Wakerly, Digital Design-Principles and Practices, 4th ed.,Pearson Prentice Hall, USA, 2006. ISBN: 0131733494.