Efficient Leakage Reduction Approach for Low Power VLSI Design Using Modified Feedback Sleeper Stack Technique

International Journal of Electronics and Communication Engineering

© 2024 by SSRG - IJECE Journal

Volume 11 Issue 3

Year of Publication : 2024

Authors : Anitha P. Bose, N. Santhi

10.14445/23488549/IJECE-V11I3P101

How to Cite?

Anitha P. Bose, N. Santhi, "Efficient Leakage Reduction Approach for Low Power VLSI Design Using Modified Feedback Sleeper Stack Technique," SSRG International Journal of Electronics and Communication Engineering, vol. 11,  no. 3, pp. 1-11, 2024. Crossref, https://doi.org/10.14445/23488549/IJECE-V11I3P101

Abstract:

In the quest for ever more power-efficient VLSI circuits, mitigating leakage power has become a paramount concern. As the demand for energy-efficient electronic devices continues to surge, low-power VLSI design has become prominent in modern semiconductor technology. One of the most significant challenges in achieving low power consumption is mitigating leakage currents, which have become a substantial contributor to power dissipation in nanoscale CMOS circuits. This paper introduces a novel approach for leakage reduction in VLSI designs. The technique builds upon the principles of traditional stackbased sleep transistors to suppress leakage currents in standby mode but introduces innovative modifications for enhanced efficiency. By strategically combining feedback mechanisms with sleep transistors, this method achieves significant leakage reduction while maintaining excellent area and performance characteristics. The suggested method is evaluated on both the NAND-3 circuit and the C17 benchmark circuit for performance comparison. The utilisation of the suggested power reduction methods involves implementing each circuit with low-Vth, high-Vth, and dual-Vth techniques. The assessment of logic circuits primarily focuses on two critical metrics: leakage power and power delay product. The outcomes of the simulations have conclusively demonstrated that the adoption of high threshold voltage transistors emerges as a highly effective strategy for mitigating static power consumption while incurring minimal delay degradation. The proposed technique holds great promise in the pursuit of ultra-low power consumption, making it a valuable addition to the toolkit of VLSI designers in an era where energy efficiency is paramount.

Keywords:

CMOS, Deep submicron technology, Leakage reduction, Nanoscale CMOS, Power dissipation, Semiconductor technology.

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