Strong-ARM Dynamic Latch Comparators: Design and Analyses on CAD Platform

International Journal of Electronics and Communication Engineering

© 2024 by SSRG - IJECE Journal

Volume 11 Issue 3

Year of Publication : 2024

Authors : Kasi Bandla, Dipankar Pal

10.14445/23488549/IJECE-V11I3P109

How to Cite?

Kasi Bandla, Dipankar Pal, "Strong-ARM Dynamic Latch Comparators: Design and Analyses on CAD Platform," SSRG International Journal of Electronics and Communication Engineering, vol. 11,  no. 3, pp. 87-95, 2024. Crossref, https://doi.org/10.14445/23488549/IJECE-V11I3P109

Abstract:

Strong-ARM Dynamic Latch Comparators are widely used in high-speed Analog-to-Digital Converters (ADCs), sense amplifiers in memory, RFID applications, and data receivers. This paper presents different methods to improve the performance of Strong-Arm latch-based comparators. The comparator’s significant features, such as power dissipation, propagation delay, offset voltage, clock feedthrough, area, and kickback noises, are discussed and compared with state-of-the-art candidate topologies. Simulation results show that the new comparator topologies of Strong-ARM Dynamic Latch proposed by these authors gave the best results. The proposed designs are tested. The simulations are carried out using UMC 180nm double metal, double poly standard CMOS process technology for a 100 MHz clock at 1.8V supply-rail on the Cadence Virtuoso EDA platform.

Keywords:

Strong-ARM, Cascode, Propagation delay, Kickback noise, Offset voltage, Power Delay Product.

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