Realization of BIST Architecture using SRAM Cell Based on Input Vector Monitoring

International Journal of Electronics and Communication Engineering

© 2015 by SSRG - IJECE Journal

Volume 2 Issue 4

Year of Publication : 2015

Authors : Miruthubashini.S ,Venkatesan.K and Kirubakaran.T

10.14445/23488549/IJECE-V2I4P114

How to Cite?

Miruthubashini.S ,Venkatesan.K and Kirubakaran.T, "Realization of BIST Architecture using SRAM Cell Based on Input Vector Monitoring," SSRG International Journal of Electronics and Communication Engineering, vol. 2,  no. 4, pp. 27-29, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I4P114

Abstract:

To perform testing during normal operation of the circuit, without forcing the circuit to go offline is concurrent BIST testing. Built-In Self Test (BIST) techniques constitute an attractive and practical solution, to solve the problem of testing VLSI circuits and systems. In this paper, we perform input vector monitoring BIST scheme, by monitoring a set of vectors called windows during its normal operation and the testing of the circuit is also carried on along with its normal operation of the circuit.

Keywords:

BIST, CUT, Concurrent, Input Vector Monitoring, Online BIST

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