A Novel Approach for Design and Simulation of Data-Driven Clock Gating Technique for Sensor Network

International Journal of Electronics and Communication Engineering

© 2015 by SSRG - IJECE Journal

Volume 2 Issue 5

Year of Publication : 2015

Authors : Kutagal Bavajan and D. Devi Sasikala

10.14445/23488549/IJECE-V2I5P112

How to Cite?

Kutagal Bavajan and D. Devi Sasikala, "A Novel Approach for Design and Simulation of Data-Driven Clock Gating Technique for Sensor Network," SSRG International Journal of Electronics and Communication Engineering, vol. 2,  no. 5, pp. 37-41, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I5P112

Abstract:

In our reality, correspondence frameworks assume an essential part in normal life. In remote and wired correspondence frameworks, signals are to be upsampled at the transmitter. Advanced up converter (DUC) is a specimen rate transformation method which is generally used to expand the testing rate of an info signal. The advanced up converter changes over low inspected computerized baseband sign to a pass band signal. In this paper, we are going to outline and execute a low commotion advanced up converter on a FPGA (Field Programmable Gate Show). In computerized up converter, the data sign is sifted and changed over to higher testing rate and after that it is tweaked with the bearer sign produced from the direct advanced synthesizer (DDS). This framework comprises of a cascadedintegrator brush (CIC) introduction channel, fell integrator brush remuneration channel, multiplier and a direct advanced synthesizer. The fell integrator brush insertion channel performs upsampling of the info sign and the fell integrator brush pay channel is utilized to repay the misfortunes of CIC channel by sifting the info signal. The Multiplier is utilized for duplicating the upsampled sign from CIC channel with the transporter sign produced from DDS and gives the DUC yield. In this DUC, the info sign is upsampled at the rate of eight. Here, two advanced up converters are utilized andconnected with a snake as a part of request to get a low clamor yield signal. The coding of this work is done in VHDL. The reproduction and utilitarian check is completed utilizing Xilinx ISE and FPGA execution is done utilizing Virtex 5.

Keywords:

Digital Up Converter,Cascade Integrator Comb Filter, Field Programmable Gate Array, Direct Digital Synthesizer

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