Simulation and Analysis of Reversible Fault-Tolerant Gate-Based Configurable Logic Blocks for Robust FPGA Architecture and Computational Efficiency

International Journal of Electronics and Communication Engineering

© 2025 by SSRG - IJECE Journal

Volume 12 Issue 3

Year of Publication : 2025

Authors : Ravi L.S, Naveen K.B, Dankan Gowda V, Nagesh R

10.14445/23488549/IJECE-V12I3P106

How to Cite?

Ravi L.S, Naveen K.B, Dankan Gowda V, Nagesh R, "Simulation and Analysis of Reversible Fault-Tolerant Gate-Based Configurable Logic Blocks for Robust FPGA Architecture and Computational Efficiency," SSRG International Journal of Electronics and Communication Engineering, vol. 12,  no. 3, pp. 68-78, 2025. Crossref, https://doi.org/10.14445/23488549/IJECE-V12I3P106

Abstract:

The need to design reliable systems that offer higher computing power for less power has led to the integration or implementation of reversible computing principles in FPGA design. This paper concentrates on enhancing an advanced Configurable Logic Block (CLB) architecture using Reversible Fault-Tolerant Gates (RFTG). The proposal's goals include control over the power dissipation, the performance characteristics, and the reliability of FPGA modules. Incorporating Lookup Tables (LUTs), multiplexers, D- latch, master-slave flip-flop, and built-in test circuit, the proposed HDL allows multiple technologies of nanometres of sizes (180nm, 90 nm, and 45 nm) that are aimed toward arithmetically inclined circuit like adder and subtractor. Simulation results confirm the improvements in the function evaluations, quantum cost, delay, and the number of garbage outputs compared with the current techniques. It provides a basis for building reliable, scalable and energy-efficient FPGAs applicable to, say, aerospace and digital systems.

Keywords:

Reversible computing, Fault-tolerant design, Configurable Logic Block, FPGA, Energy-efficient architecture, Quantum cost, Nanometre technologies, Arithmetic applications, Computational efficiency.

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