Implementation of Rijindael’s Encryption and Decryption Algorithm using FPGA
| International Journal of Electronics and Communication Engineering |
| © 2015 by SSRG - IJECE Journal |
| Volume 2 Issue 5 |
| Year of Publication : 2015 |
| Authors : Vishakha.M.Gajbhiye and V.G Puranik |
10.14445/23488549/IJECE-V2I5P121
How to Cite?
Vishakha.M.Gajbhiye and V.G Puranik, "Implementation of Rijindael’s Encryption and Decryption Algorithm using FPGA," SSRG International Journal of Electronics and Communication Engineering, vol. 2, no. 5, pp. 67-70, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I5P121
Abstract:
Encryption is employed in communications systems to safeguard data being transmitted over a channel from being intercepted and skim by unauthorised parties. This protection is achieved by changing the initial message ( plain text) into associate degree encoded kind (cipher text) that seems to be a random stream of symbol 2 architectures and VLSI implementations of the AES Proposal, Rijndael, are bestowed . These various architectures are operated each for encryption and decryption method. They cut back the specified hardware resources and come through high-speed performance. Their style philosophy is totally totally different. the primary uses feedback logic and reaches a output price adequate to 259 Mbit/sec. It performs expeditiously in applications with low lined space resources. The second design is optimized for high-speed performance exploitation pipelined technique. Its output will reach three.65 Gbit/sec. The ensuing VLSI circuits come through information rates considerably high, supporting each operation method (encryption/decryption) of Rijndael algorithmic program. they will be applied to online encryption/ decryption wants of high speed networking protocols like Asynchronous Transfer Mode (ATM) or Fiber Distributed information Interface (FDDI).
Keywords:
Rijindael’s algorithm, AES, DES, FPGA, matlab.
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