Area Efficient Architecture for TCAM using Hybrid Partitioned SRAM
| International Journal of Electronics and Communication Engineering |
| © 2015 by SSRG - IJECE Journal |
| Volume 2 Issue 7 |
| Year of Publication : 2015 |
| Authors : Sreelekshmi S and Pooja S. Mohan |
10.14445/23488549/IJECE-V2I7P109
How to Cite?
Sreelekshmi S and Pooja S. Mohan, "Area Efficient Architecture for TCAM using Hybrid Partitioned SRAM," SSRG International Journal of Electronics and Communication Engineering, vol. 2, no. 7, pp. 26-29, 2015. Crossref, https://doi.org/10.14445/23488549/IJECE-V2I7P109
Abstract:
Ternary content addressable memories are special type of memories that provides very highspeed search operation. But when comparing with traditional Static Random Access Memory (SRAM), Ternary Content Addressable Memory (TCAM) suffers from certain drawbacks like low bit density, high cost, low scalability and lack of available flavors. So here is an area efficient novel architecture for TCAM based on hybrid partitioned SRAM. The design is equipped with gated-clocking scheme so that efficient power management is achieved. The architecture was verified by VHDL
Keywords:
Field programmable gate array(FPGA), Linear Priority Encoder, Hybrid Partitioning, Gated clocking, ternary content addressable memory
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