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Volume 13 | Issue 6 | Year 2026 | Article Id. IJECE-V13I6P115 | DOI : https://doi.org/10.14445/23488549/IJECE-V13I6P115

High-Speed Approximate Adder Architecture for Image Processing Applications

Dande Parameswara Upendranath, Krishnanaik Vankdoth

Received Revised Accepted Published
17 Mar 2026 16 Apr 2026 15 May 2026 27 Jun 2026

Citation :

Dande Parameswara Upendranath, Krishnanaik Vankdoth, "High-Speed Approximate Adder Architecture for Image Processing Applications," International Journal of Electronics and Communication Engineering, vol. 13, no. 6, pp. 187-194, 2026. Crossref, https://doi.org/10.14445/23488549/IJECE-V13I6P115

Abstract

Approximate computing offers a revolutionary way to handle the increasing needs of computationally demanding tasks like video processing and recognition by permitting a certain level of error within acceptable bounds. Enhancing the adder can result in notable decreases in latency, power consumption, and area. This study’s strategy improves the accuracy of the adder by approximating the moderately important region. With just a slight loss in accuracy, power efficiency is increased, and additional hardware complexity is decreased by introducing a constant correction term in the constant region. The results show that the proposed design works, with power improvements of up to 67.3% over existing designs.

Keywords

Low Power, Approximate Computing, Image Processing Applications.

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