A Survey on Matrix Based Error Detection and Correction Codes

International Journal of Electrical and Electronics Engineering

© 2025 by SSRG - IJEEE Journal

Volume 12 Issue 2

Year of Publication : 2025

Authors : Kavya Cherakula, Varadarajan Sourirajan

10.14445/23488379/IJEEE-V12I2P116

How to Cite?

Kavya Cherakula, Varadarajan Sourirajan, "A Survey on Matrix Based Error Detection and Correction Codes," SSRG International Journal of Electrical and Electronics Engineering, vol. 12,  no. 2, pp. 146-156, 2025. Crossref, https://doi.org/10.14445/23488379/IJEEE-V12I2P116

Abstract:

Semiconductor memories are prone to various types of faults, such as stuck-at faults, memory faults, etc, that manifest as errors. As the data is usually stored in the memory in matrix form, the error correction capability is maximised by using Matrix codes with a minimal number of parity bits and improvement in code rate. The survey of codes extracted include MPC, 3D, HVD, HVDD, DMC, MDMC, PMC, HDMC, OPC, PrMC and MPrMC codes. The results are obtained by modeling in Verilog HDL using Xilinx Vivado Tool 28nm Zynq FPGA (XC7Z100-2FFG1156). These methods are evaluated for redundant bits, code rate, area in terms of LUTs, power dissipation, delay, etc. The MPrMC method – 2 Code uses reduced bit overhead by atleast 25.77% to 70.59%, increases code rate by 8.38% to 57.16%, decreases area occupied by 45.98% to 52.04% for encoder, 7.43% to 13.37% for decoder, decreases PDP by 19.69% to 51.74% for encoder and 33.67% to 40.97% for decoder. Hence, the MPrMC code proves to be a better choice in all aspects but trades off the area utilised.

Keywords:

Code rate, Errors, Faults, Matrix codes, Radiation, Redundant bits.

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